A 1.25–20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application

Abstract

A high-frequency high performance frequency synthesizer designed for 40-Gb/s SerDes is presented. In this work, a 20 GHz frequency is generated using a 10 GHz phase locked loop (PLL) that improves its power and area efficiency. The fundamental 10 GHz signal, its sufficiently strong second harmonic at 20 GHz, the divided outputs at 5/2.5/1.25 GHz are generated simultaneously using an integer-N PLL and a mixer-based frequency doubler. The proposed mixer uses an inductorless fully-differential active-inductor topology to reduce the area with marginal tradeoff in phase noise. The frequency synthesizer was designed and implemented in CMOS 55-nm technology. The doubler is integrated with a 10 GHz LC-VCO based PLL having an active area of $390 \times 520\,\upmu \mathrm{m}^2$ (without pads), with a phase noise of −115 dBc/Hz at 10 MHz offset frequency and consumes 40.08 mW power from 1.2 V power supply, one of the lowest among the reported literature. The mixer has a maximum conversion gain (CG) of 5.46 dB, 1-dB compression point ($P_{-1dB}$) of −2.5 dBm and an input-referred third-order intercept point (IIP3) of −3.2 dBm. The proposed inductorless mixer-based doubler occupies an active area of $55 \times 35\,\upmu \mathrm{m}^2$ and it adds < 1.5 dB phase noise at 20 GHz. The frequency synthesizer was used in a Serializer of the 40-Gb/s SerDes transmitter which is critical in back-haul communication for IoT and cyber physical systems.