Abstract
This paper presents a method for translating a subset of VDM-SL to higher order logic, more specifically the PVS specification language. This method has been used in an experiment where we have taken three existing, relatively large specifications written in VDM-SL, hand-translated these to PVS and then tried to type check the results. This is not as simple as it may sound since the specifications make extensive use of subtypes, via type invariants and pre- and postconditions, and therefore type checking necessarily involves some theorem proving. In trying to prove some of these type checking conditions, a worrying number of errors were identified in the specifications.
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© 1996 Springer-Verlag Berlin Heidelberg
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Agerholm, S. (1996). Translating specifications in VDM-SL to PVS. In: Goos, G., Hartmanis, J., van Leeuwen, J., von Wright, J., Grundy, J., Harrison, J. (eds) Theorem Proving in Higher Order Logics. TPHOLs 1996. Lecture Notes in Computer Science, vol 1125. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0105393
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DOI: https://doi.org/10.1007/BFb0105393
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