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Performance-Driven Clustering

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Encyclopedia of Algorithms
  • 78 Accesses

Years and Authors of Summarized Original Work

  • 1993; Rajaraman, Wong

Problem Definition

Circuit partitioning consists of dividing the circuit into parts, each of which can be implemented as a separate component (e.g., a chip) that satisfies the design constraints. The work of Rajaraman and Wong [5] considers the problem of dividing a circuit into components, subject to area constraints, such that the maximum delay at the outputs is minimized.

A combinational circuit can be represented as a directed acyclic graph G = (V, E), where V is the set of nodes and E is the set of directed edges. Each node represents a gate in the network and each edge (u, v) in E represents an interconnection between gates u and v in the network. The fanin of a node is the number of edges incident into it, and the fanout of a node is the number of edges incident out of it. A primary input (PI) is a node with fanin 0, while a primary output (PO) is a node with fanout 0. Each node has a weight and a delay...

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Recommended Reading

  1. Cong J, Ding Y (1992) An optimal technology mapping algorithm for delay optimization in lookup-table based fpga design. In: Proceedings of IEEE international conference on computer-aided design, Santa Clara, pp 48–53

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  4. Pan P, Karandikar AK, Liu CL (1998) Optimal clock period clustering for sequential circuits with retiming. IEEE Trans Comput-Aided Des Integr Circuits Syst 17:489–498

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  5. Rajaraman R, Wong DF (1995) Optimum clustering for delay minimization. IEEE Trans Comput-Aided Des Integr Circ Syst 14:1490–1495

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  6. Yang HH, Wong DF (1997) Circuit clustering for delay minimization under area and pinconstraints. IEEE Trans Comput-Aided Des Integr Circ Syst 16:976–986

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Correspondence to Rajmohan Rajaraman .

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Rajaraman, R. (2016). Performance-Driven Clustering. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_291

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