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NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications

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Handbook of Hardware/Software Codesign

Abstract

In this chapter we define what a mixed-time-criticality system is and what its requirements are. After defining the concepts that such systems should follow, we described CompSOC, which is one example of a mixed-time-criticality platform. We describe, in detail, how multiple resources, such as processors, memories, and interconnect, are combined into a larger hardware platform, and especially how they are shared between applications using different arbitration schemes. Following this, the software architecture that transforms the single hardware platform into multiple virtual execution platforms, one per application, is described.

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Abbreviations

AHB:

Advanced High-performance Bus

ASIC:

Application-Specific Integrated Circuit

AXI:

Advanced eXtensible Interface

BD:

Budget Descriptor

CCSP:

Credit-Controlled Static Priority

CDC:

Clock Domain Crossing

CM:

Communication Memory

DLMB:

Data Local Memory Bus

DMA:

Direct Memory Access

DMAMEM:

DMA Memory

DMEM:

Data Memory

DRAM:

Dynamic Random-Access Memory

ELF:

Executable and Linkable Format

ET:

Execution Time

ETSCH:

Extended TSCH

FBSP:

Frame-Based Static Priority

FIFO:

First-In First-Out

FPGA:

Field-Programmable Gate Array

GALS:

Globally Asynchronous Locally Synchronous

ILMB:

Instruction Local Memory Bus

IMEM:

Instruction Memory

I/O:

Input/Output

IP:

Intellectual Property

IPB:

Intellectual Property Block

KPN:

Kahn Process Network

MAC:

Media Access Control

MMIO:

Memory-Mapped I/O

MPSoC:

Multi-Processor System-on-Chip

NI:

Network Interface

NoC:

Network-on-Chip

PLB:

Processor Local Bus

RR:

Round Robin

RT:

Response Time

RTOS:

Real-Time Operating System

SI:

Scheduling Interval

SoC:

System-on-Chip

SPI:

Serial Peripheral Interface

SRAM:

Static Random-Access Memory

TDM:

Time-Division Multiplexing

TFT:

Thin-Film Transistor

TIFU:

Timer, Interrupt, and Frequency Unit

TSCH:

Time-Synchronised Channel Hopping

TTA:

Transport-Triggered Architecture

UART:

Universal Asynchronous Receiver/Transmitter

VEP:

Virtual Execution Platform

WCET:

Worst-Case Execution Time

WCRT:

Worst-Case Response Time

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Acknowledgements

The development of CompSOC has been partially funded by European grants, including CATRENE CT217 RESIST; ARTEMIS 621429 EMC2, 621353 DEWI, 621439 ALMARVI, and ECSEL 692455 ENABLE-S3.

Author information

Authors and Affiliations

  1. Eindhoven University of Technology, Eindhoven, The Netherlands

    Kees Goossens, Martijn Koedam, Andrew Nelson, Shubhendu Sinha, Sven Goossens, Yonghui Li, Gabriela Breaban, Reinier van Kampenhout, Rasool Tavakoli, Juan Valencia, Hadi Ahmadi Balef, Benny Akesson, Sander Stuijk, Marc Geilen, Dip Goswami & Majid Nabi

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  1. Kees Goossens
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  2. Martijn Koedam
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  3. Andrew Nelson
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  4. Shubhendu Sinha
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  5. Sven Goossens
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  6. Yonghui Li
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  7. Gabriela Breaban
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  8. Reinier van Kampenhout
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  10. Juan Valencia
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  11. Hadi Ahmadi Balef
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  12. Benny Akesson
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  14. Marc Geilen
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  15. Dip Goswami
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  16. Majid Nabi
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Corresponding author

Correspondence to Kees Goossens .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Goossens, K. et al. (2017). NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_17

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