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Testability analysis at switch level for CMOS circuits

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Abstract

In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach. The complexity of the algorithm is nearly linear.

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References

  1. Shen Li, Testability analysis for digital circuits: a survey,Computer Research and Development (in Chinese), 9 (1988), 18–24.

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  2. The Special Issue on Switch-Level Techniques,IEEE Design & Test of Computers,4:4(1987).

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  3. M.A. Breuer & A.D. Friedman, TEST/80—A Proposal for Advanced Automatic Test Generation System, AUTOTESTCON 1977, 305–312.

  4. L.H. Goldstein, Controllability/Observability analysis of digital circuits,IEEE Trans. on Circuits and Systems, 9 (1979), 685–693.

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Authors and Affiliations

  1. CAD Laboratory, Institute of Computing Technology, Academia Sinica, Beijing, China

    Shen Li

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  1. Shen Li
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Shen, L. Testability analysis at switch level for CMOS circuits. J. of Compt. Sci. & Technol. 5, 197–202 (1990). https://doi.org/10.1007/BF02943425

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  • DOI: https://doi.org/10.1007/BF02943425

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