Abstract
An application to perform a visual simulation of a machine based on MIPS is presented in this paper. The advantage of this system in relation to conventional simulators is that the simulation engine is the result of a real simulation under a VHDL development environment, so that hardware description can be modified and simulated in several ways to test and study its performance. So, it is possible to join the versatility of a commercial VHDL development tool with the simple handling of a graphic environment. In addition, an assembler language has been defined to write simple applications in order to test the simulated computer.
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© 2000 Kluwer Academic Publishers
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Álvarez Llorente, J.M., Pavó Pulido, N., Ballesteros Rubio, J. (2000). A Visual Simulation Environment for MIPS Based on VHDL. In: Ortega, M., Bravo, J. (eds) Computers and Education in the 21st Century. Springer, Dordrecht. https://doi.org/10.1007/0-306-47532-4_6
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DOI: https://doi.org/10.1007/0-306-47532-4_6
Publisher Name: Springer, Dordrecht
Print ISBN: 978-0-7923-6577-8
Online ISBN: 978-0-306-47532-0
eBook Packages: Springer Book Archive