Conclusions
This chapter focused on frequency synthesizers intended to be used in phasemodulation communication systems. An analysis of the residual phase deviation of PLL frequency synthesizers was presented, departing from a simplified model which was used to relate the phase noise of the building blocks to the total residual phase deviation. The simple model was enhanced with an investigation of the effect of the phase margin and of the open-loop bandwidth on the residual phase deviation. The results were used in the implementation of adesign methodology for single-loop PLLs and for multi-loop PLLs. A double-loop tuning system architecture, intended to be used in L-band satellite receivers, was then described. It consists of a wide-band loop for phase noise reduction of the integrated oscillator and of a second loop which supplies the wide-band loop with a clean reference signal in the VHF range. The remaining of the chapter presented the architecture and circuit implementation of building blocks for wide-band loops: a low-power 3 GHz modular programmable divider and a 300 MHz phase-frequency detector/charge-pump combination. The circuits were implemented in a conservative BiCMOS technology which provided npn transistors with an fT of 9 GHz and lateral pnp transistors with an fT of 200 MHz. The innovative circuit topology of the charge-pump enabled dead-zone free operation at frequencies in excess of the fT of the pnp transistors which composed its output stage.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J.D. van der Tang, D. Kasperkovitz and A. Bretveld, “A 65 mW, 0.4–2.3 GHz bandpass filter for satellite receivers,” in IEEE Custom Integrated Circuits Conf. (CICC), 2000, pp. 383–386.
A.A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communication,” IEEE Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410, Dec. 1995.
C.J.M. Verhoeven, “A High-Frequency Electronically Tunable Quadrature Oscillator,” IEEE Journal of Solid-State Circuits, vol. 27, no. 7, pp. 1097–1100, July 1992.
A. Rofougoran et al., “A 900 MHz CMOS LC Oscillator with Quadrature Outputs,” in IEEE International Solid-State Circuits Conf. (ISSCC), 1996, pp. 316–317.
J.D. van der Tang and D. Kasperkovitz, “A 0.9–2.2 GHz Monolithic Quadrature Mixer-Oscillator for Direct Conversion Satellite Receivers,” in IEEE International Solid-State Circuits Conf. (ISSCC), 1997, pp. 88–89.
T. Wakimoto and S. Konaka, “A 1.9-GHz Si Bipolar Quadrature VCO with Fully-Integrated LC Tank,” in IEEE Symposium on VLSI Circuits, 1998, pp. 30–31.
M.Q. Tavares, PLL frequency synthesizers: phase noise issues and wide band loops, Ph.D. Thesis, Institut National des Sciences Appliquees de Lyon, France, 1999.
P.W.J. van de Ven et al., “An Optimally Coupled 5 GHz Quadrature Oscillator,” in IEEE Symposium on VLSI Circuits, 2001, pp. 115–118.
R. Corvaja and S. Pupolin, “Phase Noise Effects in QAM Systems,” in IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 1997, vol. 8, pp. 452–452.
J. Majewsky, “New Methode of Phase Noise and Intermodulation DIstortion Reduction in High-order QAM Systems,” in Conference on Microwaves, Radar and Wireless Communications, 2000, vol. 13, pp. 258–264.
W.P. Robins, Phase Noise in Signal Sources, 9. IEE Telecomm., London, 2nd edition, 1996.
A. Hajimiri and T. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
E.A.M. Klumperink et al., “Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 994–1001, July 2000.
U.L. Rohde, RF and Microwave Digital Frequency Synthesizers, Wiley, New York, 1997.
C.S. Vaucher and D. Kasperkovitz, “A Wide-Band Tuning System for Fully Integrated Satellite receivers,” IEEE Journal of Solid-State Circuits, vol. 33, no. 7, pp. 987–997, July 1998.
F.M. Gardner, “Charge-Pump Phase-lock Loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849–1858, Nov. 1980.
A.K. Hadjizada et al., “TV and TVS AT Mixer-oscillator PLL IC,” IEEE Transactions on Consumer Electronics, vol. 41, no. 3, pp. 942–945, Aug. 1995.
EUTELSAT, Earth Station Standard EESS 500, 1996.
Philips Semiconductors, TSA5059 Datasheet — 2.7GHz I2-C-bus controlled low phase noise frequency synthesizer, 2000.
W.G. Kasperkovitz, “Digital Shift Register,” US Patent 5,113,419 (U.S. Philips Corporation), 1992.
A. Hill and J. Surber, “The PLL Dead Zone and How to Avoid It,” RF Design, pp. 131–134, Mar. 1992.
J. Craninckx and M. Steyaert, “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2054–2065, Dec. 1998.
M. Soyuer and R.G. Meyer, “Frequency Limitations of a Conventional Phase-Frequency Detector,” IEEE Journal of Solid-State Circuits, vol. 25, no. 4, pp. 1019–1022, Aug. 1990.
Rights and permissions
Copyright information
© 2003 Kluwer Academic Publishers
About this chapter
Cite this chapter
(2003). Wide-Band Tuning System Architectures. In: Architectures for RF Frequency Synthesizers. The International Series in Engineering and Computer Science, vol 693. Springer, Boston, MA. https://doi.org/10.1007/0-306-47955-9_4
Download citation
DOI: https://doi.org/10.1007/0-306-47955-9_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7120-1
Online ISBN: 978-0-306-47955-7
eBook Packages: Springer Book Archive