Silicon On Insulator Memories

Summary

Silicon-on-insulator technology creates many interesting challenges in memory design and test. It is key to understand and factor in the parasitic bipolar and history effects inherent to memories in SOI. There are greater challenges due to increased loading along a bit line as a function of the data type stored in the cells along a column. The impact of history on cell stability must be considered as well. With careful design and test, performance advantages can be gained and robust circuitry can be implemented in silicon-on-insulator technology.

“...was to him but a memory of loveliness in far days and of his first grief⃜”