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References
C. Eisenhut & J. W. Klein, “SIMOX Voltage References for Applications up to 275°C using the Threshold Difference Principle”, Proceedings 1997 IEEE International SOI Conference, Oct 1997, pp. 110–1.
A. Marshall, “Operating Power ICs at 200 degrees”, IEEE Power Electronics Specialists Conference, Madrid, Spain 1992, pp. 1033–9
Appendix 1: (11.3)
S. K. H. Fung, et. al., “Impact of the Gate-to-Body Tunneling Current on SOI History Effect”, 2000 IEEE International SOI Conference, pp. 122–3.
T. Efland, et. al., “The load dump (automobiles)”, IEEE Workshop on Electronic Applications in Transportation, 1990, pp. 73–78.
A. Marshall & J. Devore, “Dual switch-mode regulator IC” International Solid-State Circuits Conference (ISSCC), 1995. pp. 52–53.
D. W. Dobberpuld, et. al., “A 200-MHz 64-b dual-issue CMOS microprocessor”, IEEE J. Solid-State Circuits, vol. 27, Nov. 1992, pp. 1555–1567.
R. Berger, et. al., “A 1.3-GHz SOI CMOS Test Chip for Low-Power High-Speed Pulse Processing”, IEEE Journal of Solid State Circuits, Vol. 33, No. 8, Aug 1998, pp. 1259–6.
J-H. Lee & Y-J. Park, “High speed SOI buffer Circuit with the Efficient Connection of Subsidiary MOSFET’s for Dynamic Threshold Control”, Proceedings 1997 IEEE International SOI Conference, Oct 1997, pp. 152–3.
C. Chen, et. al., “Single-transistor latch in SOI MOSFET’s”, IEEE Electron Device Letters, vol. 9, 1988, pp. 636–8.
J. Gautier & A.J. Auberton-Herve, “A Latch Pheonomenon in buried N-body SOI NMOSFET’s”, IEEE Electron Device Letter, vol. 12, 1991, pp. 372–4.
A. Marshall & F. Carvajal, “Power+ Logic Methodology Applied to a Six Output Power Driver”, IEEE 1993 Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, Minnesota, Oct 4–5, 1993. IEEE Cat No. 93CH3315-9, pp. 72–75.
“Flip-chip bumping on 300mm wafers”, European Semiconductor, Feb 2000, p38
J. Klein, “Bottomless SO-8 Package Boosts MOSFET Performance”, Power Conversion and Intelligent Motion, May 2000, pp. 110.
Y. Wang et.al., “Electrothermal Modeling of ESD Diodes in Bulk-Si and SOI Technologies,” EOS/ESD Symp. Proc., pp. 430–436, 2000.
S. Ramaswamy et. al., “EOS/ESD Protection Circuit Design for Submicron SOI Technology,” EOS/ESD Symp. Proc., pp. 212–217, 1995.
G. G. Shahidi, et. al., “CMOS scaling for high performance applications” IBM J. Res. Development, vol. 39, Jan./Mar. 1995, pp. 229–244.
S. H. Voldman, “The State of the Art of Electrostatic Discharge Protection: Physics, Technology, Circuits, Design, Simulation, and Scaling”, IEEE Journal of Solid State Circuits, Vol 34, No. 9, Sept. 1999, pp. 1272–1282.
P. Raha, et. al., “EOS/ESD Reliability of Partially Depleted SOI Technology”, IEEE Trans. Electron Device., Vol. 46, No. 2, Feb. 1999, pp. 429–431.
S. Voldman, et. al., “Dynamic Threshold Body and Gate-Coupled SOI ESD Protection Networks,” Jounral of Electrostatics, 44, pp. 239–255, 1998.
C. Duvvury, et. al., “ESD design for deep submicron SOI technology,” Symp. VLSI Technology Dig. Tech. Papers, 1996, pp. 194–195.
J. C. Smith, et. al., “ESD protection circuits for TFSOI technology,” Proc. 1996 IEEE Int. SOI Conf., 1996, pp. 170–171.
S. Voldman et. al., “CMOS-on-SOI ESD protection networks”, Proc. EOSIESD Symp., Sept. 1996, pp. 291–301.
M. Chan, et. al., “Comparison of ESD protection capability of SOI and bulk CMOS output buffers” Proc. IRPS, 1994.
K. Verhaege, et. al., “Double snapback in SOI NMOSFET’s and its application for SOI ESD protection”, IEEE Electron Device Lett., vol. 14, July 1993, pp. 326–328.
“Analysis of snapback in SOI NMOSFET’s and its use for an SOI ESD protection circuit”, Proc. of the IEEE SOI Conf., 1992, pp. 140–141.
T. P. Ma & P. V. Dressendorfer, Editors, “Ionizing Radiation Effects in MOS Devices and Circuits”, New York: Wiley, 1989.
Y. Minami, et. al., “Direct Observation of Gate Oxide Destruction due to BOX Breakdown in SOI” 2000 IEEE International SOI Conference, Oct. 2000, pp. 130–131.
S. Chakravarty & P.J. Thadikaran, “Introduction to IDDQ Testing”, Kluwer Academic Publishers, 1997
B. T. Mitchell, “Operating-Extremes Test Improves Reliability”, Test and Measurement World, Nov 2000, pp. 45–50.
A. Krstic & K-T Cheng, “Delay Fault Testing for VLSI Circuits”, Kluwer Academic Publishers, Boston, 1998.
K. Baker, et. al., “Defect-based delay testing of Resistive Viascontacts, a critical evaluation”, International Test Conference ITC 1999, pp. 467–476
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(2003). Global Design Issues. In: SOI Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-48161-8_11
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