Summary
This chapter discussed details about the topics of verification. The chapter began with implementation of messaging, which is the mechanism of communication to the users. The next topic was the design of monitors and their usefulness. An example monitor code was also provided. BFMs were discussed next, which form the substance of the test environment. The last topic was stimulus generation through BFMs either by directed or random fashion. Examples were discussed for the different illustrations.
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© 2004 Springer Science + Business Media, Inc.
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(2004). Verification. In: Verilog: Frequently Asked Questions. Springer, Boston, MA. https://doi.org/10.1007/0-387-22899-3_3
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DOI: https://doi.org/10.1007/0-387-22899-3_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-22834-1
Online ISBN: 978-0-387-22899-0
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