Abstract
Chips containing reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based systems. Using embedded cores enables the design of high-complexity systems-on-chip with densities as high as millions of gates on a single die. The increase in the use of pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately, test solutions need to be incorporated into individual cores and then the tests from individual cores need to be scheduled and assembled into a chip level test strategy. However with the increased usage of cores from multiple and diverse sources, it is essential to create standard mechanisms to make core test plug-and-play possible. This chapter presents in general the challenges of testing core-based system-chips and describes their corresponding test solutions. It concentrates on the common test requirements and strategies
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References
V.D. Agrawal, C.J. Lin, P.W. Rutkowski, S. Wu, Y. Zorian, ‘‘Built-In Self-Test for Digital Integrated Circuits’’, AT&T Technical Journal, Vol. 73, No. 2, p. 30, March 1994.
F. Beenker, B. Bennetts, L. Thijssen, ‘‘Testability Concepts for Digital ICs – Macro Test Approach’’ Volume 3 of Frontiers in Electronics Testing. Kluwer Academic Publishers, Boston, 1995.
B. Bennetts, ‘‘A Design Strategy for System-on-a-chip testing’’, Electronic Products, June 1997, pp. 57-59.
S. Bhatia, T. Gheewala, P. Varma, ‘‘A Unifying Methodology for Intellectual Property and Custom Logic Testing’’, Proc. of International Test Conference, Oct. 1996, pp. 639-648.
R. Chandramouli, S. Pateras, ‘‘Testing Systems on a Chip’’, IEEE Spectrum, pp. 42-47, Nov. 1996.
K. De, ‘‘Test Methodology for Embedded Cores which Protects Intellectual Property’’, VTS 97, pp. 2-9.
R.K. Gupta, Y. Zorian, ‘‘Introduction to Core-based System Design’’, IEEE Design & Test of Computers, Vol. 14, No. 4, Oct.-Dec. 1997.
S.G. Hemmady, T.L. Anderson, Y. Zorian, ‘‘Verification and Testing of Embedded Cores’’, Proc. Design SuperCon, On-Chip Design, S122-1-19, Jan. 1997.
M. Hunt, J.A. Rowson, ‘‘Blocking in a System on a Chip’’, IEEE Spectrum, pp. 35-41, Nov. 1996.
B.K. Koenemann, K. Wagner, ‘‘Test Sockets: A Test Framework for System-On-Chip Designs’’, IEEE TTTC Embedded Core Test TAC Study Group, April 1997.
J. Lipman, ‘‘The Hard Facts about Soft Cores’’, EDN, pp. 35, Sept. 2, 1996.
G. Maston, ‘‘Structuring STIL for Scan Test Generation based on STIL’’, Porc. Int’l Test Conference, 1997.
J. Monzel, ‘‘Low Cost Testing of System-On-Chip’’, Proc. Digest of 1st IEEE International TECS, Nov. 1997.
B.T. Murray, J.P. Hayes, ‘‘Testing IC s: Getting to the Core of the Problem’’, IEEE Computer, Vol. 29, No. 11, pp. 32-38, Nov. 1996.
G. Smith, ‘‘Test and System Level Integration’’, IEEE Design & Test of Computers, Vol. 14, No 4, Oct.-Dec. 1997.
N. A. Touba, B. Pouya, ‘‘Testing Embedded Cores Using Partial Isolation Rings’’, Proc. of the 15th IEEE VLSI Test Symposium, pp. 10-15, April, 1997.
‘‘Virtual Socket Interface Architectural Document’’, VSI Alliance, Nov. 1996.
L. Whetsel, ‘‘An IEEE 1149.1 based Test Access Architecture for ICs with Embedded IP Cores’’, Porc. Int’l Test Conference, Nov. 1997.
P. Wohl, V.T. Williston and J. Waicukauski, ‘‘A Unified Interface for Scan Test Generation based on STIL’’, Proc. Int’l Test Conference, Nov. 1997.
Y. Zorian, ‘‘A Distributed BIST Control Scheme for Complex VLSI Devices’’, Proc. of the 11th IEEE VLSI Test Symposium, p. 6-11, April 1993.
Y. Zorian, ‘‘Test Requirements for Embedded Core-based Systems and IEEE P1500’’, Proc. of IEEE International Test Conference, Nov. 1997.
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© 2006 Springer
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Zorian, Y. (2006). Embedded Core-based System-on-Chip Test Strategies. In: Reis, R., Lubaszewski, M., Jess, J.A. (eds) Design of Systems on a Chip: Design and Test. Springer, Boston, MA. https://doi.org/10.1007/0-387-32500-X_11
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DOI: https://doi.org/10.1007/0-387-32500-X_11
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