Timing Analysis for a Combinational Stage

Summary

In this chapter, we have seen how the delay of a single combinational stage, with many coupled interconnect elements, can be found. A stage may consist of linear interconnect elements and nonlinear elements related to MOS devices. Efficient techniques for taking advantage of the linearities while taking the nonlinearities into account have been presented, including the notion of an effective capacitance. This provides the basis for circuit-level analysis, where the delays of combinational stages are added up to systematically determine the worst-case delay of a combinational circuit.