Abstract
Current paper proposes an efficient alternative for traditional gate-level fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, it is pointed out that simultaneous to simulation on SSBDDs, the set of potential fault locations can be significantly reduced. In addition, algorithms for deductive and concurrent fault simulation on SSBDD models are introduced in the paper. While full implementation of the new SSBDD based algorithms needs to be carried out, the paper presents experimental data revealing the advantages of the proposed data structure in the fault simulation process.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ulrich, E.G., Baker, T.: Concurrent Simulation of Nearly Identical Digital Networks. Computer 7, 39–44 (1974)
Armstrong, D.B.: A Deductive Method for Simulating Faults in Logic Circuits. IEEE Trans. Comput. C-21, 464–471 (1972)
Seth, S.C., Pan, L., Agrawal, V.D.: Predict-Probabilistic Estimation of Digital Circuit Testability, Dig. Papers FTCS-15, pp. 220-225 (June 1985)
Antreich, K.J., Schulz, M.H.: Accelerated Fault Simulation and Fault Grading in Combinational Circuits. IEEE Trans. on CAD CAD-6(5), 704–712 (1987)
Ubar, R.: Test Generation for Digital Circuits Using Alternative Graphs. In: Proc. Tallinn Technical University, Tallinn TU, Tallinn, Estonia, vol. (409), pp. 75–81 (1976)
Ubar, R.: Test Synthesis with Alternative Graphs. IEEE Design & Test of Comp. Spring, 48–59 (1996)
Jutman, A., Peder, A., Raik, J., Tombak, M., Ubar, R.: Structurally synthesized binary decision diagrams. In: 6th International Workshop on Boolean Problems, Freiberg, Germany, September 23-24, pp. 271–278 (2004)
Liaw, H.-T., Lin, C.-S.: On the OBDD-representation of general Boolean functions. IEEE Trans. on Computers C-41(6), 61–664 (1992)
Ubar, R., Vassiljeva, T., Raik, J., Jutman, A., Tombak, M., Peder, A.: Optimization of Structurally Synthesized BDDs. In: Proc of the 4th IASTED International Conference on Modelling, Simuation, and Optimization MSO 2004, Kauai, Hawaii, USA, August 17-19, pp. 234–240 (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Raik, J., Ubar, R., Devadze, S., Jutman, A. (2005). Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. In: Dal Cin, M., Kaâniche, M., Pataricza, A. (eds) Dependable Computing - EDCC 5. EDCC 2005. Lecture Notes in Computer Science, vol 3463. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11408901_25
Download citation
DOI: https://doi.org/10.1007/11408901_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-25723-3
Online ISBN: 978-3-540-32019-7
eBook Packages: Computer ScienceComputer Science (R0)