Abstract
Dynamically reconfigurable computing systems (DRCS) provides an intermediate tradeoff between flexibility and performance of computing systems design. Unfortunately, designing DRCS has a highly complex and formidable task. The lack of tools and design flows discourage designers from adopting the reconfigurable computing technology. A UML-based design flow for DRCS is proposed in this article. The proposed design flow is targeted at the execution speedup of functional algorithms in DRCS and at the reduction of the complexity and time-consuming efforts in designing DRCS . In particular, the most notable feature of the proposed design flow is a HW-SW partitioning methodology based on the UML 2.0 sequence diagram, called Dynamic Bitstream Partitioning on Sequence Diagram (DBPSD). To prove the feasibility of the proposed design flow and DBPSD partitioning methodology, an implementation example of DES (Data Encryption Standard) encryption/decryption system is presented in this article.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bondalapati, K., Prasanna, V.K.: Reconfigurable computing systems. Proceedings of the IEEE 90(7), 1201–1217 (2002)
Compton, K., Hauck, S.: Reconfigurable computing: A survey of systems and software. ACM Computing Surveys 34(2), 171–210 (2002)
Booch, G., Rumbaugh, J., Jacobson, I.: Unified Modeling Language User Guide. Addison-Wesley, Reading (1999)
Niaz, I.A., Tanaka, J.: Mapping UML statecharts to Java code. In: Proceedings of the IASTED International Conference on Software Engineering (SE 2004), February 2004, pp. 111–116 (2004)
Rhapsody case tool reference manual, I-Logix Inc., http://www.ilogix.com
Beierlein, T., Frőhlich, D., Steinbach, B.: UML-based co-design for run-time reconfigurable architectures. In: Proceedings of the Forum on Specification and Design Languages (FDL 2003), September 2003, pp. 5–19 (2003)
Beierlein, T., Frőhlich, D., Steinbach, B.: Model-driven compilation of UML-models for reconfigurable architectures. In: Proceedings of the Second RTAS Workshop on Model-Driven Embedded Systems (MoDES 2004) (May 2004)
Fleischmann, J., Buchenrieder, K., Kress, R.: A hardware/software prototyping environment for dynamically reconfigurable embedded systems. In: Proceedings of the 6th International Workshop on Hardware/Software Codesign, pp. 105–109. IEEE Computer Society, Los Alamitos (1998)
Fleischmann, J., Buchenrieder, K., Kress, R.: Java driven codesign and prototyping of networked embedded systems. In: Proceedings of the 36th ACM/IEEE Design Automation Conference (DAC 1999), pp. 794–797. ACM Press, New York (1999)
Robertson, I., Irvine, J.: A design flow for partially reconfigurable hardware. ACM Transactions on Embedded Computing Systems 3(2), 257–283 (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tseng, CH., Hsiung, PA. (2005). UML-Based Design Flow and Partitioning Methodology for Dynamically Reconfigurable Computing Systems. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_49
Download citation
DOI: https://doi.org/10.1007/11596356_49
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
eBook Packages: Computer ScienceComputer Science (R0)