Abstract
In this paper we consider mesh connected computers with reconfigurable buses. The architecture consists of N 1/2 × N 1/2 PEs, with PEs in each row and column connected to a shared bus. The buses are partitionable using N 1/2-1 switches embedded on each bus. This provides efficient global communication patterns for a variety of partitions of the mesh connected computer. We illustrate the suitability of the architecture by demonstrating efficient parallel solution to several graph problems and low level vision problems which have low interprocessor communication requirements. Compared to known reconfigurable architectures and other parallel architectures such as mesh of trees and pyramids, the proposed organization has low area requirement and simple switch control while providing fast parallel solutions to several problems.
This research was supported in part by USC Faculty Research and Innovation Fund and by DARPA under coutract F 33615-84-K-1404 monitored by the Air Force Wright Aeronautical Laboratory.
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Reisis, D., Kumar, V.K.P. (1988). VLSI arrays with reconfigurable buses. In: Houstis, E.N., Papatheodorou, T.S., Polychronopoulos, C.D. (eds) Supercomputing. ICS 1987. Lecture Notes in Computer Science, vol 297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18991-2_41
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DOI: https://doi.org/10.1007/3-540-18991-2_41
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