Abstract
This paper discusses the design and implementation of a profile-based power-aware compiler using dynamic voltage scaling. The compiler identifies program regions where the CPU can be slowed down without resulting in a significant overall performance loss. Two strategies have been implemented in SUIF2. The single-region strategy slows down a single region for energy savings, while the multiple-region strategy slows down as many regions as needed. A comparison of both strategies based on six SPECfp95 benchmarks shows that in five cases, the energy-delay product was comparable. In the remaining case, the multiple-region strategy was significantly better. Both strategies achieved energy savings of up to 48% for the five programs at the slowdown between 1% and 16%, and energy savings of 74% for the multiple regions vs. 50% for the single region strategy for the remaining program at the slowdown up to 21%.
This research was partially supported by NSF CAREER award CCR-9985050.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
N. AbouGhazaleh, D. Mossé, B. Childers, and R. Melhem. Toward the placement of power management points in real time applications. In Proceedings of the Workshop on Compilers and Operating Systems for Low Power, September 2001.
A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau. Profile-based dynamic voltage scheduling using program checkpoints in the COPPER framework. In Proceedings of Design, Automation and Test in Europe Conference, March 2002.
T. Ball and J. Larus. Using paths to measure, explain, and enhance program behavior. IEEE Computer, 31(7), 2000.
D. Burger. Hardware Techniques to Improve the Performance of the Processor/Memory Interface. PhD thesis, Computer Science Department, University of Wisconsin-Madison, 1998.
D. Burger and T. Austin. The SimpleScalar tool set version 2.0. Technical Report 1342, Computer Science Department, University of Wisconsin-Madison, June 1997.
J. Czyzyk, M. Mesnier, and J. Moré. The NEOS server. IEEE Journal on Computational Science and Engineering, 5(3), July–September 1998.
R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1277–1284, September 1996.
C.-H. Hsu and U. Kremer. Compiler-directed dynamic voltage scaling based on program regions. Technical Report DCS-TR-461, Department of Computer Science, Rutgers University, November 2001.
C.-H. Hsu, M. Hsiao, and U. Kremer. Compiler-directed dynamic frequency and voltage scheduling. In Workshop on Power-Aware Computer Systems, November 2000.
M. Irwin. Low power design: From soup to nuts. Tutorial at the International Symposium on Computer Architecture, June 2000.
T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In International Symposium on Low Power Electronics and Design, pages 197–202, August 1998.
D. Kroft. Lockup-free instruction fetch/prefetch cache organization. In Proceedings of the 18th International Symposium on Computer Architecture, pages 81–87, May 1981.
S. Lee and T. Sakurai. Run-time voltage hopping for low-power real-time systems. In Proceedings of the 37th Conference on Design Automation, pages 806–809, June 2000.
S. Leyffer. Integrating SQP and branch-and-bound for mixed integer nonlinear programming. Computational Optimization and Applications, 18(3):295–309, March 2001.
J. Lorch and A. Smith. Improving dynamic voltage algorithms with PACE. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems, June 2001.
A. Manzak and C. Chakrabarti. Variable voltage task scheduling algorithms for minimizing energy. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.
D. Mossé, H. Aydin, B. Childers, and R. Melhem. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Workshop on Compiler and Operating Systems for Low Power, October 2000.
T. Mudge. Power: A first class design constraint for future architectures. In Proceedings of International Conference on High Performance Computing, December 2000.
T. Pering, T. Burd, and R. Brodersen. The simulation and evaluation of dynamic voltage scaling algorithms. In Proceedings of 1998 International Symposium on Low Power Electronics and Design, pages 76–81, August 1998.
S. Raje and M. Sarrafzadeh. Variable voltage scheduling. In International Symposium on Low Power Electronics and Design, pages 9–14, August 1995.
D. Shin and J. Kim. A profile-based energy-efficient intra-task voltage scheduling algorithm for hard real-time applications. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.
D. Shin, J. Kim, and S. Lee. Intra-task voltage scheduling for low-energy hard real-time applications. IEEE Design and Test of Computers, 18(2), March/April 2001.
P. Stanley-Marbell, M. Hsiao, and U. Kremer. A hardware architecture for dynamic performance and energy adaptation. In Workshop on Power-Aware Computer Systems, February 2002.
SUIF. Stanford University Intermediate Format.
V. Swaminathan and K. Chakrabarty. Investigating the effect of voltage switching on low-energy task scheduling in hard real-time systems. In Asia South Pacific Design Automation Conference, January/February 2001.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hsu, CH., Kremer, U. (2003). Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_13
Download citation
DOI: https://doi.org/10.1007/3-540-36612-1_13
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-01028-9
Online ISBN: 978-3-540-36612-6
eBook Packages: Springer Book Archive