Abstract
We describe a static profiling methodology to extract hot-spots from netlists. Hot-spots are small regular sub-circuits the optimization of which has a big impact on the final result. We have built a tool that can extract and characterize hot-spots from large netlists very quickly. The tool can be used to direct human attention on portions of circuits that need hand-optimization, as well as to automatically direct efforts of FPGA tools. We show impressive throughput improvements when compiling to the PipeRench reconfigurable architecture and use hot-spots to enable fast architectural design space exploration for FPGAs by predicting the FPGA CLB structure that produces the best final area-delay. Our prediction is fairly accurate and only takes a few hours as compared to weeks for an exhaustive analysis. We also demonstrate better results when targeting FPGAs with heterogeneous CLBs.
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Cadambi, S., Goldstein, S.C. (2001). Static Profile-Driven Compilation for FPGAs. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_12
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DOI: https://doi.org/10.1007/3-540-44687-7_12
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