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Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates

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Integrated Circuit Design (PATMOS 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1918))

Abstract

In this communication adiabatic and conventional gates with a different fan-in are modeled and analytically compared. The comparison is carried out assuming both an assigned power supply and setting it to minimize power consumption. The analysis leads to simple expressions, which allow to understand how the power advantage of adiabatic logic changes by increasing the fan-in of the implemented gate. The analytical results were validated by means of Spice simulations using a 0.8 μm CMOS technology.

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References

  1. A. Matsuzawa, “Low-Voltage And Low-Power Circuit Design For Mixed Analog/Digital Systems In Portable Equipment,” IEEE Jour. of Solid-State Circuits, no. 4, pp. 470–486, April 1994.

    Google Scholar 

  2. W. Athas, L. Svensson, J. Koller, N. Tzartzanis, E. Ying-Chin Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. on VLSI, Vol. 2, N. 4, pp. 398–407, December 1994.

    Article  Google Scholar 

  3. L. Svensson, “Adiabatic Switching,” in Low Power Digital CMOS Design, A. Chandrakasan, R. Brodersen, Kluwer Academic Publisher, 1995.

    Google Scholar 

  4. W. Athas, “Energy-Recovery CMOS,” in Low Power Digital Design Methodologies, J. Rabey, M. Pedram, Eds., Kluwer Academic Publisher, 1995.

    Google Scholar 

  5. V. Oklobdzija, D. Maksimovic, F. Lin, “Pass-Transistor Adiabatic Logic Using Single Power-Clock Supply,” IEEE Trans on CAS part II, Vol. 44, N. 10, pp. 842–846, Oct. 1997.

    Article  Google Scholar 

  6. W. Athas, N. Tzartzanis, L. Svensson, L. Peterson, “A Low-Power Microprocessor Based on Resonant Energy,” IEEE Jour. of Solid-State Circ., Vol. 32, No. 11, pp. 1693–1701, Nov. 1997.

    Article  Google Scholar 

  7. M. Knapp, P. Kindlmann, M. Papaefthymiou, “Design and Evaluation for Adiabatic Arithmetic Units,” Analog Integrated Circuit and Signal Processing, Vol. 14, pp. 71–79, 1997.

    Article  Google Scholar 

  8. Chun-Keung Lo, P. Chan, “Design of Low Power Differential Logic Using Adiabatic Switching Technique,” Proc. ISCAS’98, Monterey, June 1998.

    Google Scholar 

  9. M. Alioto, G. Palumbo, “Adiabatic Gates: A Critical Point of View,” Proc. ECCTD’99, Stresa, August 1999.

    Google Scholar 

  10. M. Alioto, G. Palumbo, “Evaluation of power consumption in adiabatic circuits,” Proc. ISCAS2000, Genève, May 2000.

    Google Scholar 

  11. J. Rabaey, Digital Integrated Circuits (A Design Perspective), Prentice Hall, 1996.

    Google Scholar 

  12. D. Standley and J. L. Wyatt, Jr. “Improved signal delay bounds for RC tree networks,” VLSI Memo, no. 86-317, Massachusetts Institute of Technology, Cambridge, Massachusetts, May 1986.

    Google Scholar 

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Author information

Authors and Affiliations

  1. DEES (Dipartimento Elettrico Elettronico e Sistemistico), UNIVERSITA’ DI CATANIA, Viale Andrea Doria 6, I-95125, CATANIA, ITALY

    M. Alioto & G. Palumbo

Authors
  1. M. Alioto
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  2. G. Palumbo
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Editor information

Editors and Affiliations

  1. Dept.of Electrical & Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece

    Dimitrios Soudris

  2. Institute for Communication Theory and Signal Processing, University of Hanover, Appelstr.4, 30167, Hanover, Germany

    Peter Pirsch

  3. Institute for Microelectronic Systems, University of Hanover, Appelstr.4, 30167, Hanover, Germany

    Erich Barke

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© 2000 Springer-Verlag Berlin Heidelberg

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Alioto, M., Palumbo, G. (2000). Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_28

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  • DOI: https://doi.org/10.1007/3-540-45373-3_28

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41068-3

  • Online ISBN: 978-3-540-45373-4

  • eBook Packages: Springer Book Archive

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