Abstract
Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. However, there are problems associated with this method, of slow learning speeds and large systems, which are serious obstacles to utilizing EHW in various kinds of practical applications. To overcome these problems, we have developed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm (GA) hardware, reconfigurable hardware logic, and the control logic. With this chip, we have successfully executed GA learning and hardware reconfiguration. In this paper, we describe the architecture, functions, and a performance evaluation of the chip. We show that its learning speed is considerably faster than with software.
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Iwata, M., Kajitani, I., Liu, Y., Kajihara, N., Higuchi, T. (2001). Implementation of a Gate-Level Evolvable Hardware Chip. In: Liu, Y., Tanaka, K., Iwata, M., Higuchi, T., Yasunaga, M. (eds) Evolvable Systems: From Biology to Hardware. ICES 2001. Lecture Notes in Computer Science, vol 2210. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45443-8_4
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DOI: https://doi.org/10.1007/3-540-45443-8_4
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