Abstract
A method for estimating the power on architecture-level is described. Originally based on simulations with data sequences, the method is extended by an simulation-free approach. The statistical properties required for the underlying Dual-Bit-Type model are propagated through the circuit. The necessary computation formulas are presented. For both approaches, the model accuracy for base modules as for signal processing applications is comparably low.
The work presented is supported by the German Research Foundation, Deutsche Forschungsgemeinschaft (DFG), within the research initiative “VIVA” under contract number PI 169/14.
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Freimann, A. (2002). Probabilistic Power Estimation for Digital Signal Processing Architectures. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_46
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DOI: https://doi.org/10.1007/3-540-45716-X_46
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