Abstract
Reconfigurable Computing (RC) has already been proved as a cost-efficient solution for rapid prototyping and some low-volume applications. Today, RC also gains importance in the context of embedded systems. However, mature and fully developed reconfigurable logic solutions for such systems are still missing. The primary reasons for this are the intrinsic cost of reconfigurable logic, and dedicated process technologies that reconfigurable designs are usually based on. In this paper, we present a novel reconfigurable logic core which addresses these issues. A logic cell architecture of the core has been tuned to a single application domain only (application-specific kernels in DSP applications). This allowed a reduction of the required amount of routingre sources by 28% compared with a commercial FPGA architecture. The core has been implemented in a standard CMOS 0.13μm process technology.
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References
Adelante Technologies, “DSP” Hardware Implementation using Behavioural Synthesis, Internal presentation, http://www.adelantetech.com.
Agarwala M., Balsara P.T., An Architecture for a DSP Field-Programmable Gate Array, IEEE Transactions on VLSI, Vol. 3, No. 1, March 1995.
Altera, Embedded Programmable Logic Family. FLEX 10K, Data sheet, September 2000, ver. 2.10.
Altera, Stratix Programmable Logic Device Family, Data sheet, February 2002, ver.1.0.
Atmel, AT40K FPGAs with FreeRAM, Data sheet, January 1999.
Betz V., Rose J., Marquardt A., Architecture and CAD for Deep-submicron FPGAs, Kluwer Academic Publisher, 1999.
Brown S.D., Francis R.J., Rose J., Vranesic Z.G., Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.
Chow P., Seo S.O., Rose J., Chung K., Páez-Monzón G., Rahardja I., The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout, IEEE Transactions on VLSI, Vol. 7, No. 3, September 1999.
Dehon A., Reconfigurable Architectures for General-Purpose Computing, AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, September 1996.
DeHon A., The Density Advantage of Configurable Computing, Special Issue of IEEE Design and Test, April 2000.
Bauer T.J., Lookup Tables which Doubles as Shift Registers, Patent Application No. 754 421, Xilinx, Filed November 1996.
Betz V., Rose J., VPR: A New Packing, Placement and Routing Tool for FPGA Research, International Workshop on Field Programmable Logic and Applications, 1997.
George V., Low Energy Field-Programmable Gate Array, Ph.D. Thesis, University of California, Berkeley, 2000.
He J., Rose J., Advantages of Heterogeneous Logic Block Architectures for FPGAs, IEEE Custom Integrated Circuits Conference, San Diego, May 1993.
Kaviani A., Vranesic D., Brown S., Computational Field Programmable Architecture, IEEE Custom Integrated Circuits Conference, May 1998.
Kaviani A., Novel Architectures and Synthesis Methods for High Capacity Field Programmable Devices, Ph. D. Thesis, University of Toronto, Canada, 1999.
Leijten-Nowak K., van Meerbergen J. L., Applying the Adder Inverting Property in the Design of Cost-Efficient Reconfigurable Logic, IEEE Midwest Symposium on Circuits and Systems, Dayton, USA, August 2001.
Marshall A., Stansfield T., Kostarnov I., Vuillemin J., Hutchings B., A Reconfigurable Arithmetic Array for Multimedia Applications, ACM/SIGDA International Symposium on FPGAs, Monterey, February 1999.
Miller N.L., Quigley S.F., A Reconfigurable Integrated Circuit for High Performance Computer Arithmetic, IEE, 1998.
Rabaey J., Digital Integrated Circuits. A Design Perspective, Prentice Hall, 1996.
Rabaey J., Reconfigurable Processing: The Solution to Low-Power Programmable DSP, IEEE International Conference on Acoustic, Speech and Signal Processing, April 1997.
Singh S., Rose J., Lewis D., Chung K., Chow P., Optimisation of Field-Programmable Gate Array Logic Block Architecture for Speed, IEEE Custom Integrated Circuits Conference, May 1990.
Xilinx, XC4000E and XC4000X Series Field Programmable Gate Arrays, Data sheet, January 1999.
Xilinx, Virtex 2.5V Field Programmable Gate Arrays, Data sheet, January 2000.
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Leijten-Nowak, K., van Meerbergen, J.L. (2002). Embedded Reconfigurable Logic Core for DSP Applications. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_11
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DOI: https://doi.org/10.1007/3-540-46117-5_11
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