Abstract
This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex® FPGA from Xilinx™. The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a look-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation, the circuit was downloaded to a Virtex FPGA. Results show that not only it is possible to implement many embryonic cells on one device, but also the reconfiguration strategies allow a level of fault tolerance to be achieved.
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© 2000 Springer-Verlag Berlin Heidelberg
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Ortega, C., Tyrrell, A. (2000). A Hardware Implementation of an Embryonic Architecture Using Virtex® FPGAs. In: Miller, J., Thompson, A., Thomson, P., Fogarty, T.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2000. Lecture Notes in Computer Science, vol 1801. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46406-9_16
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DOI: https://doi.org/10.1007/3-540-46406-9_16
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