The VLSI layout problem in various embedding models

Abstract

In 1984 Kramer and van Leeuwen proved a fundamental complexity result of VLSI layout theory. They showed that the so-called General Layout Problem, i.e. the problem of embedding a graph into a grid of minimum area is NP-hard, even for connected (but not necessarily planar) graphs.

VLSI circuits (or large parts of them) are typically modelled by planar graphs, but Kramer and van Leeuwen used a family of non-planar graphs for their reduction and they posed the complexity of minimum area layouts of planar connected graphs as an open problem.

We

• close a gap in their proof,

• extend the NP-hardness result to the more realistic class of planar connected graphs and

• show this for three different embedding models, including the Manhattan and the knock-knee model.

This work was partially supported by the ESPRIT II Basic Research Actions Program of the EC under contract no. 3075 (project ALCOM).