Abstract
This paper describes an implementation of a novel systolic array for sequence alignment on the SPLASH reconfigurable logic array. The systolic array operates in two phases. In the first phase, a sequence comparison array due to Lopresti [1] is used to compute a matrix of distances which is stored in local RAM. In the second phase, the stored distances are used by the alignment array to produce a binary encoding of the sequence alignment. Preliminary benchmarks show that the SPLASH implementation performs several orders of magnitude faster than implementation on supercomputers.
Supported during Summer 1991 by an NIH Summer Internship and afterwards by an NSF Graduate Fellowship.
Supported by NSF grant MIP-9020570.
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References
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© 1993 Springer-Verlag Berlin Heidelberg
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Hoang, D.T., Lopresti, D.P. (1993). FPGA implementation of systolic sequence alignment. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_43
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DOI: https://doi.org/10.1007/3-540-57091-8_43
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