Abstract
Lower bounds are developed for the processor-time tradeoffs of machines such us linear arrays and two-dimensional meshes, which are compatible with the physical limitation on speed propagation of messages. It is shown that, under this limitation, parallelism and locality combined may yield speedups superlinear in the number of processors. The results are obtained by means of on a novel technique, called the “closed-dichotomy-size technique”, designed to obtain lower bounds to the computation time for networks of processors, each of which is equipped with a local hierarchical memory.
Supported in part by the ESPRIT III Basic Research Programme of the EC under contract No. 9072 (Project GEPPCOM), by the Italian Ministry of University and Research, and by Brown University.
Supported in part by NSF Grant CCR94-00232 and ONR Contract N 00014-91-J-4052, ARPA order 2225.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
A. Aggarwal, B. Alpern, A.K. Chandra and M. Snir. A Model for Hierarchical Memory. In Proc. of the 19th ACM Symposium on Theory of Computing, (1987), 305–314.
A. Aggarwal, A.K. Chandra and M. Snir. Communication Complexity of PRAMs. Theoretical Computer Science, 71:3–28, 1990.
G. Bilardi and F.P. Preparata. Area-Time Lower-Bound Techniques with Application to Sorting. Algorithmica, 1:65–91, 1986.
G. Bilardi and F.P. Preparata. Horizons of Parallel Computing. In Proc. of INRIA 25th Anniversary Symposium, invited paper, 1992, LNCS Springer-Verlag. To appear in Journal on Parallel and Distributed Computing.
G. Bilardi and F.P. Preparata. Processor-Time Tradeoffs under Bounded-Speed Message Propagation: Part I, Upper Bounds. TR, CS Dept., Brown University, May 1995.
G. Bilardi and F.P. Preparata. Processor-Time Tradeoffs under Bounded-Speed Message Propagation: Part II, Lower Bounds. TR, CS Dept., Brown University, May 1995.
R.P. Brent. The Parallel Evaluation of General Arithmetic Expressions. Journal of the ACM, (21)2:201–206, 1974.
S.A. Cook and R.A. Reckhow. Time Bounded Random Access Machines. Journal of Comput. System Science, 7:354–375, 1973.
J.W. Hong and H.T. Kung. I/O Complexity: The Red-Blue Pebble Game. In Proc. of the 13th ACM Symposium on Theory of Computing, (1981), 326–333.
J.E. Savage. Space-Time Tradeoffs in Memory Hierarchies. TR, Dept. of Comp.Sci., Brown University, 1995.
L. Snyder. Type Architectures, Shared Memory, and the Corollary of Modest Potential. Annual Review of Computer Science, 1:289–317, 1986.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1995 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bilardi, G., Preparata, F.P. (1995). Lower bounds to processor-time tradeoffs under bounded-speed message propagation. In: Akl, S.G., Dehne, F., Sack, JR., Santoro, N. (eds) Algorithms and Data Structures. WADS 1995. Lecture Notes in Computer Science, vol 955. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60220-8_46
Download citation
DOI: https://doi.org/10.1007/3-540-60220-8_46
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-60220-0
Online ISBN: 978-3-540-44747-4
eBook Packages: Springer Book Archive