Abstract
Serial data-path circuits are often more difficult to analyze than their parallel counterparts. The major reason is data and operations are spread over time. Here the strength of formal verification is demonstrated with verification of classical serial pipeline multipliers. The designer's informal notions of how to interpret the design are formally captured in well-defined functions and standard mathematical notation. A linear-time temporal logic is found to be useful for analyzing such circuits; temporal operators are succinct in expressing certain operating conditions that are otherwise verbose, and temporal laws and operators enable us to work more efficiently in a higher level of reasoning.
This work was supported by the NY State Center for Advanced Technology in Computer Applications and Software Engineering (CASE) at Syracuse University. The authors are grateful to Anand Chavan for his help with the GDT tools for getting layouts and simulations for this work.
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© 1995 Springer-Verlag Berlin Heidelberg
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Kim, J.D., Chin, SK. (1995). Formal verification of serial pipeline multipliers. In: Thomas Schubert, E., Windley, P.J., Alves-Foss, J. (eds) Higher Order Logic Theorem Proving and Its Applications. TPHOLs 1995. Lecture Notes in Computer Science, vol 971. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60275-5_68
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DOI: https://doi.org/10.1007/3-540-60275-5_68
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