Abstract
This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC architecture. The framework combines the monitors with a well-tailored design methodology that explores how the Autonomic SoC (ASoC) can cope with malfunctioning subcomponents.
This work is funded by DFG within the priority program 1183 “Organic Computing”.
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LEON VHDL code is available at www.gaisler.com.
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© 2006 International Federation for Information Processing
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Bouajila, A., Bernauer, A., Herkersdorf, A., Rosenstiel, W., Bringmann, O., Stechele, W. (2006). Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. In: Pan, Y., Rammig, F.J., Schmeck, H., Solar, M. (eds) Biologically Inspired Cooperative Computing. BICC 2006. IFIP International Federation for Information Processing, vol 216. Springer, Boston, MA . https://doi.org/10.1007/978-0-387-34733-2_11
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DOI: https://doi.org/10.1007/978-0-387-34733-2_11
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