Cellular Array-Based Delay-Insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

Complementary metal-oxide semiconductor (CMOS)has been the dominant technology for implementing VLSI systems because it provides a good trade-off high speed and small area.The continuous decrease in transistor feature size has been pushing the CMOS process to its physical limits caused by ultra-thin gate oxides,short channel effects, doping fluctuations, and the unavailability of lithography in nanoscale range. To continue the size/speed improvement trends according to Moore's Law, nanoelectronic and molecular electronic devices are needed. A significant amount of research has been done in nanoscale computing system design [1–5].Although recent research have resulted in the development of basic logic elements and simple circuits in nanoscale,there are still debates on what logic style and architecture will be the best for nanocomputers. A family of asynchronous logic called delay-insensitive circuits has drawn attention in recent years. The advantages of delay-insensitive circuits include flexible timing requirement,low power, high modularity, etc. These characteristics fit the needs of nanoscale computing. Cellular arrays have an ideal architecture for implementing delay-insensitive circuits in nanoscale; they have highly regular structures,simple cell behavior,and flexible scalability [5,6]. The regular structure together with delay-insensitive circuit style makes cellular arrays a viable option for implementing nanocomputing systems.