Dynamic random access memory (DRAM) is a type of random access memory that uses charge stored on individual capacitors to hold data within an integrated circuit. Since these capacitors are non-ideal and suffer from parasitic leakages, the information eventually fades and the charge stored requires periodic refresh. Because of this refresh requirement, this memory type is classified as dynamic, in contrast to static random access memory (Fig. 5.1a) where a cross-coupled pair maintains the data state.
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References
J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Processor Based Built-In Self Test for Embedded DRAM," IEEE J. Solid-State Circuits 33, No. 11, November 1998, 1731–1740
T. Yabe, S. Miyano, K. Sato, M. Wada, R. Haga, O. Wada, M. Enkaku, T. Hojyo, K. Mimoto, M. Tazawa, T. Ohkubo, and K. Numata, “A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator," IEEE J. Solid-State Circuits 33, No. 11, November 1998, 1752–1757.
NeoMagic Corporation, 3250 Jay St., Santa Clara, CA 95054. The NeoMagic memory and logic graphics processors were introduced in 1993; see http://www.neomagic.com/about/ history.asp.
G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni, C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh, M. Vincent, T. von Reyn, and J. Zimmerman, “A 1 MB, 100 MHz Integrated L2 Cache Memory with 128b Interface and ECC Protection," Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), 1996, pp. 370–371.
A guide to IBM embedded DRAM offerings can be found at http://www.ibm.com/chips/ techlib
S. Crowder, R. Hannon, H. Ho, D. Sinitsky, S. Wu, K. Winstel, B. Khan, S. R. Stiffler, and S. S. Iyer, “Integration of Trench DRAM into a High Performance 0.18 um Logic Technology with Copper BEOL," International Electron Devices Meeting, Digest of Technical Papers, 1998, pp. 1017–1020.
T. Obremski, “Advanced Non-Concurrent BIST Architecture for Deep Sub-Micron Embedded DRAM Macros," Ph.D. Dissertation, University of Vermont, Burlington, May 2001.
N. Watanabe, F. Morishita, Y. Taito, A. Yamazaki, T. Tanizaki, K. Dosaka, Y. Morooka, F. Igaue, K. Furue, Y. Nagura, T. Komoike, T. Morihara, A. Hachisuka, K. Arimoto, and H. Ozaki, “An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced on Chip Tester," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2001, pp. 388–389, 469.
R. Matick, et al., “Logic-based eDRAM: Origins and rationale for use", IBM Jour. Res & Dev. Vol. 49, No 1, January 2005, pp. 145–165.
E. Cohen, et al., “A 64B CPU Pair: Dual and Single-Processor Chips", 2005 ISSCC Dig. Tech. Papers, 2005, pp. 106–107.
S. Naffziger, et al., “The implementation of a 2-core Multi-Threaded Itanium-Family Processor", 2005 ISSCC Dig. Tech. Papers, 2005, pp. 182–183.
R. H. Dennard, “Field Effect Transistor Memory," U.S. Patent 3,387,286, June 4, 1968.
T. Kirihata, P. Parries, D. Hanson, H. Kim, J. Golz, G. Fredeman, R. Rajeevakumar, J. Griesmer, N. Robson, A. Cestero, M. Wordeman, and S. Iyer, “An 800 MHz Embedded DRAM with a Concurrent Refresh Mode," Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), 2004, Digest of Technical Papers, 1, 2004, pp. 206–523.
M. Kumar, M. D. Steigerwalt, B. L. Walsh, T. L. Doney, D. Wildrick, K. A. Bard, D. M. Dobuzinsky, P. A. McFarland, C. E. Schiller, B. Messenger, S. E. Rathmill, A. R. Gasasira, P. C. Parries, S. S. Iyer, S. E. Chaloux, and H. L. Ho, “A Simple and High-Performance 130 nm SOI EDRAM Technology Using Floating-Body Pass-Gate Transistor in Trench-Capacitor Cell for System-on-a-Chip (SoC) Applications,“ Proceedings of the IEEE International Electron Devices Meeting (IEDM), 2003, Technical Digest, 2003, pp. 17.4.1–17.4.4.
E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability," J. Design Automat. Fault- Tolerant Comput. 2, May 1978, 165–178.
J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Built-In Self Test for Embedded DRAM," Proceedings of the IEEE North Atlantic Test Workshop, West Greenwich, RI, 1997, pp. 19–27.
R. McConnell, U. Moller, and D. Richter, “How We Test Siemens’ Embedded DRAM Cores," Proceedings of the International Test Conference, 1998, pp. 1120–1125.
R. Aitken, “On-Chip Versus Off-Chip Test: An Artificial Dichotomy," Proceedings of the International Test Conference, 1998, p. 1146.
J. Dreibelbis, J. Barth, Jr., R. Kho, and T. Kalter, “An ASIC Library Granular DRAM Macro with Built-In Self Test," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1998, pp. 74–75.
H. A. Bonges III, R. D. Adams, A. J. Allen, R. Flaker, K. S. Gray, E. L. Hedberg, W. T. Holman, G. M. Lattimore, D. A. Lavalette, K. Y. T. Nguyen, and A. L. Roberts, “A 576 K 3.5 ns Access BiCMOS ECL Static Ram with Array Built-in Self Test," IEEE J. Solid-State Circuits 27, No. 4, April 1992, 649–656.
P. Jakobsen, J. Dreibelbis, G. Pomichter, D. Anand, J. Barth, M. Nelms, J. Leach, and G. Belansek, “Embedded DRAM Built In Self Test and Methodology for Test Insertion," Proceedings of the International Test Conference, 2001, pp. 975–984.
J. Barth, et al., “A 300 MHz multi-banked DRAM Macro featuring GND Sense, bit-line twisting and direct reference cell write," IEEE International Solid-State Circuits Conference, vol. XLV, February 2002, pp. 156–157.
J. Barth, et al., “A 500 MHz Multi-Banked Compilable DRAM Macro with Direct Write and Programmable Pipeline", 2004 ISSCC Dig. Tech. Papers, 2004, pp. 204–205.
Y. Taito, et al., “A High Density Memory for SoC with a 143 MHz SRAM Interface Using Sense- Synchronized- Read/Write", IEEE International Solid-State Circuits Conference, vol. XLVI, February 2003, pp. 306–307.
H. Pilo, et al., “A 5.6 ns Random Cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM Interface", IEEE International Solid-State Circuits Conference, vol. XLVI, February 2003, pp. 308-309.
M. Ouellette, et al., “On-chip repair and ATE-independent fusing methodology", IEEE International Test Conference Proceedings, October 2002, pp. 178–186.
S. Iyer, et al., “Embedded DRAM: Technology Platform for Blue Gene/L chip", IBM Jour. Res & Dev. Vol. 49 NO. 2/3 MARCH/MAY 2005, pp. 333–350.
Top 500 Supercomputer Sites, “TOP500 List – November 2007," http://www.top500.org/ list/2007/11/100.
J. Clabes, et al., “Design and Implementation of the Power5 Micro Processor", 2004 ISSCC Dig. Tech. Papers, 2004, pp. 56–57.
G. Wang, et al., “A 0.127 μm2 High Performance 65 nm SOI Based embedded DRAM for on-Processor Applications", 2006 IEDM, 2006.
D. Weiss, et al., “The on-chip 3-MB Subarray-based third-level cache on an Itanium microprocessor", 2002 ISSCC Dig. Tech. Papers, 2002, pp. 112–113.
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Barth, J. (2009). Embedded DRAM in Nano-scale Technologies. In: Zhang, K. (eds) Embedded Memories for Nano-Scale VLSIs. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-88497-4_5
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