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REACT: An Integrated Tool for the Design of Dependable Computing Systems

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Foundations of Dependable Computing

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 283))

Abstract

The REliable Architecture Characterization Tool (REACT) is a generalized software testbed for analyzing a variety of fault-tolerant multiprocessor systems. REACT abstracts a system at the architectural level and performs automated life testing through simulated fault-injection to accurately and efficiently measure dependability. It integrates detailed system, workload, and fault/error simulation models that have been derived, in part, from the published results of computer performance studies and low level fault-injection experiments.

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References

  1. Agarwal, A. and Gupta, A., “Memory-reference characteristics of multiprocessor applications under MACH,” in Proceedings of the 1988 Sigmetrics Conference on Measurement and Modeling of Computer Systems, pp. 215–225, ACM, May 1988.

    Google Scholar 

  2. Avižienis, A., Gilley, G. C., Mathur, F. P., Rennels, D. A., Rohr, J. A., and Rubin, D. K., “The STAR (Self-Testing And Repairing) computer; An investigation of the theory and practice of fault-tolerant computer design,” IEEE Transactions on Computers, vol. C-20, no. 11, pp. 1312–1321, Nov. 1971.

    Article  Google Scholar 

  3. Ayache, J. M. and Diaz, M., “A reliability model for error correcting memory systems,” IEEE Transactions on Reliability, vol. R-28, no. 4, pp. 310–314, Oct. 1979.

    Article  MathSciNet  Google Scholar 

  4. Bernstein, P. A., “Sequoia: A fault-tolerant tightly coupled multiprocessor for transaction processing,” IEEE Computer, vol. 21, no. 2, pp. 37–45, Feb. 1988.

    Google Scholar 

  5. Borg, A., Kessler, R. E., and Wall, D. W., “Generation and analysis of very long address traces,” in Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 270–279, ACM, May 1990.

    Google Scholar 

  6. Bratley, P., Fox, B. L., and Schrage, L. E., A Guide to Simulation. New York, NY: Springer-Verlag, 2nd ed., 1987.

    Google Scholar 

  7. Bugge, H. O., Kristiansen, E. H., and Bakka, B. O., “Trace-driven simulations for a two-level cache design in open bus systems,” in Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 250–259, ACM, May 1990.

    Google Scholar 

  8. Bunt, R. B. and Murphy, J. M., “The measurement of locality and the behaviour of programs,” The Computer Journal, vol. 27, no. 3. pp. 238–245, Aug. 1984.

    Article  Google Scholar 

  9. Bunt, R. B., Murphy, J. M., and Majumdar, S., “A measure of program locality and its application,” in Proceedings of the 1984 Sigmetrics Conference on Measurement and Modeling of Computer Systems, pp. 28–40, ACM, Aug. 1984.

    Google Scholar 

  10. Chen, C. L. and Rutledge, R. A., “Fault-tolerant memory simulator,” IBM Journal of Research and Development, vol. 28, no. 2, pp. 184–195, Mar. 1984.

    Article  Google Scholar 

  11. Chillarege, R. and Iyer, R. K., “An experimental study of memory fault latency,” IEEE Transactions on Computers, vol. 38, no. 6, pp. 869–874, June 1989.

    Article  Google Scholar 

  12. Choi, G. S. and Iyer, R. K., “FOCUS: An experimental environment for fault sensitivity analysis,” IEEE Transactions on Computers, vol. 41, no. 12, pp. 1515–1526, Dec. 1992.

    Article  Google Scholar 

  13. Clark, D. W., Bannon, P. J., and Keller, J. B., “Measuring VAX 8800 performance with a histogram hardware monitor,” in Proceedings of the 15th Annual International Symposium on Computer Architecture, pp. 176–185 ACM, May 1988.

    Google Scholar 

  14. Courtois, B., “Some results about the efficiency of simple mechanisms for the detection of microcomputer malfunctions,” in Proceedings of the 9th International Symposium on Fault-Tolerant Computing, pp. 71–74, IEEE, June 1979.

    Google Scholar 

  15. Czeck, E. W. and Siewiorek, D. P., “Effects of transient gate-level faults on program behavior,” in Proceedings of the 20th International Symposium on Fault-Tolerant Computing, pp. 236–243, IEEE, June 1990.

    Google Scholar 

  16. Emer, J.S. and Clark, D. W., “A characterization of processor performance in the VAX-11/780,” in Proceedings of the 11th Annual International Symposium on Computer Architecture, pp. 301–310, ACM, June 1984.

    Google Scholar 

  17. Heising, W. P., “Note on random addressing techniques,” IBM Systems Journal, vol. 2, pp. 112–116, June 1963.

    Google Scholar 

  18. Hennessy, J. L. and Patterson, D. A., Computer Architecture, A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 1990.

    Google Scholar 

  19. Hopkins, A. L., Smith, T. B., and Lala, J. H., “FTMP — A highly reliable fault-tolerant multiprocessor for aircraft,” Proceedings of the IEEE, vol. 66, no. 10, pp. 1221–1239, Oct. 1978.

    Google Scholar 

  20. Jewett, D., “Integrity S2: A fault-tolerant Unix platform,” in Proceedings of the 21st International Symposium on Fault-Tolerant Computing, pp. 512–519, IEEE, June 1991.

    Google Scholar 

  21. Kanawati. G. A., Kanawati, N. A., and Abraham, J. A., “FERRARI: A tool for the validation of system dependability properties,” in Proceedings of the 22nd International Symposium on Fault-Tolerant Computing, pp. 336–344, IEEE, July 1992.

    Google Scholar 

  22. Kobayashi, M. and MacDougall, M. H., “The stack growth function: Cache line reference models,” IEEE Transactions on Computers, vol. 38, no. 6, pp. 798–805, June 1989.

    Article  Google Scholar 

  23. Koo, D. Y. and Chenowith, H. B., “Choosing a practical MTTF model for ECC memory chip,” in Proceedings of the 1984 Annual Reliability and Maintainability Symposium, pp. 255–261, IEEE, Jan. 1984.

    Google Scholar 

  24. Krol, T., “(N,K) concept fault tolerance,” IEEE Transactions on Computers, vol. C-35, no. 4, pp. 339–349, Apr. 1986.

    Google Scholar 

  25. Lee, I., Iyer, R. K., and Tang, D., “Error/failure analysis using event logs from fault tolerant systems,” in Proceedings of the 21st Iniernational Symposium on Fault-Tolerant Computing, pp. 10–17, IEEE, June 1991.

    Google Scholar 

  26. Libson, M. R. and Harvey, H. E., “A general-purpose memory reliability simulator,” IBM Journal of Research and Development, vol. 28, no. 2, pp. 196–205, Mar. 1984.

    Google Scholar 

  27. Marston, D.. Memory System Reliability with ECC. Intel Corporation, Application Note AP-73, 1980.

    Google Scholar 

  28. Miremadi, G., Karlsson, J., Gunneflo, U., and Torin, J.. “Two software techniques for on-line error detection,” in Proceedings of the 22nd International Symposium on Fault-Tolerant Computing, pp. 328–335, IEEE, July 1992.

    Google Scholar 

  29. Ohlsson, J., Rimén, M., and Gunneflo, U., “A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog,” in Proceedings of the 22nd International Symposium on Fault-Tolerant Computing, pp. 316–325, IEEE, July 1992.

    Google Scholar 

  30. Shin, K. G. and Lee, Y.-H., “Measurement and application of fault latency,” IEEFj Transactions on Computers, vol. C-35, no. 4, pp. 370–375, Apr. 1986.

    Google Scholar 

  31. Siewiorek, D. P., Kini, V., Mashburn, H., McConnel, S., and Tsao, M., “A case study of C.mmp, Cm*, and C.vmp: Part I — Experiences with fault tolerance in multiprocessor systems,” Proceedings of the IEEE, vol. 66, no. 10, pp. 1178–1199, Oct. 1978.

    Google Scholar 

  32. Smith, A.J., “Cache evaluation and the impact of workload choice,” in Proceedings of the 12th Annual International Symposium on Computer Architecture, pp. 64–73, ACM, June 1985.

    Google Scholar 

  33. Spirn, J. R., Program Behavior: Models and Measurements. New York, NY: Elsevier, 1977.

    MATH  Google Scholar 

  34. Tang, D. and Iyer, R. K., “Dependability measurement and modeling of a multicomputer system,” IEEE Transactions on Computers, vol. 42, no. 1, pp. 62–75, Jan. 1993.

    Article  Google Scholar 

  35. Tang, D., Iyer, R. K., and Subramani, S. S., “Failure analysis and modeling of a VAXcluster system,” in Proceedings of the 20th International Symposium on Fault-Tolerant Computing, pp. 244–251, IEEE, June 1990.

    Google Scholar 

  36. Thiébaut, D. F., Wolf, J. L., and Stone, H. S., “Synthetic traces for trace-driven simulation of cache memories,” IEEE Transactions on Computers, vol. 41, no. 4, pp. 388–410, Apr. 1992.

    Article  Google Scholar 

  37. Toy, W. N., “Fault-tolerant design of local ESS processors,” Proceedings of the IEEE, vol. 66, no. 10, pp. 1126–1145, Oct. 1978.

    Google Scholar 

  38. Webber, S. and Beirne, J., “The Stratus architecture,” in Proceedings of the 21st International Symposium on Fault-Tolerant Computing, pp. 79–85. IEEE, June 1991.

    Google Scholar 

  39. Wiecek, C. A., “A case study of VAX-11 instruction set usage for compiler execution,” in Proceedings of the 1st International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 177–184, ACM, Mar. 1982.

    Google Scholar 

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Authors
  1. Jeffrey A. Clark
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  2. Dhiraj K. Pradhan
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© 1994 Kluwer Academic Publishers

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Clark, J.A., Pradhan, D.K. (1994). REACT: An Integrated Tool for the Design of Dependable Computing Systems. In: Foundations of Dependable Computing. The Springer International Series in Engineering and Computer Science, vol 283. Springer, Boston, MA. https://doi.org/10.1007/978-0-585-27377-8_6

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  • DOI: https://doi.org/10.1007/978-0-585-27377-8_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-9484-6

  • Online ISBN: 978-0-585-27377-8

  • eBook Packages: Springer Book Archive

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