Abstract
In this chapter, we present design level support for handling temporary and permanent errors in the NoCs. We present routing mechanisms that achieve an application-specific reliability level against temporary and permanent failures.
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© 2009 Springer Science + Business Media B.V.
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Murali, S. (2009). Fault-Tolerant Route Generation. In: Designing Reliable and Efficient Networks on Chips. Lecture Notes in Electrical Engineering, vol 34. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-9757-7_10
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DOI: https://doi.org/10.1007/978-1-4020-9757-7_10
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-9756-0
Online ISBN: 978-1-4020-9757-7
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