Abstract
Once the NoC components are made timing-error tolerant, we need to still handle other transient and permanent errors that can occur in the system, such as soft-errors. To handle such errors, we need support at the design level, as well as at the architectural level. In this chapter, we present architectural level support for fault-tolerance, while in the next chapter, we present design level support. Please note that an additional level of error protection at the application level can also be used in conjunction with these two levels.
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© 2009 Springer Science + Business Media B.V.
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Murali, S. (2009). Analysis of NoC Error Recovery Schemes. In: Designing Reliable and Efficient Networks on Chips. Lecture Notes in Electrical Engineering, vol 34. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-9757-7_9
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DOI: https://doi.org/10.1007/978-1-4020-9757-7_9
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-9756-0
Online ISBN: 978-1-4020-9757-7
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