Abstract
The through-silicon via (TSV) is composed of a conductor, also named “nail” or “plug,” crossing the Si substrate of the stacked dies [1, 2], as shown in Fig. 3.1. The conductor [common material choices include copper (Cu), tungsten (W), and polysilicon] is electrically insulated from the substrate by a dielectric layer (usually SiO2) and interconnects the metal wires of the stacked dies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Topol AW et al (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4/5):491–506
Beyne E (2006) The rise of the 3rd dimension for system integration. In: Proceedings of international interconnect technology conference, Burlingame, CA, 5–7 June, pp 1–5
Pak JS, Ryu C, Kim J (2007) Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation. In: Proceedings of international conference on electronic materials and packaging, Daejeon, 19–22 November, pp 19–22
Van Olmen J et al (2008) 3D stacked IC demonstration using a through silicon via first approach. IEDM Technical Digest pp 603–606
Kamon M, Silveira L et al (1996) FastHenry USER’S GUIDE: version 3.0, Massachusetts Institute of Technology, November, ftp://rle-vlsi.mit.edu/pub/fasthenry
Raphael Interconnect Analysis Program Reference Manual (2007) Version A-2007.09, Synopsis Inc., Mountain View, CA
Stucchi M, Perry D. Katti G. Dehaene W (2010) Test structures for characterization of through silicon vias, IEEE International Conference on Microelectronic Test Structures (ICMTS)
Sze SM (1981) Physics of semiconductor devices. John Wiley & Sons, New York
Katti G et al (2010) Electrical Characterization & Modeling of Through Silicon Via (TSV) for 3D ICs, IEEE Transactions on Electron Devices, Volume 57, Issue 1; Jan, pp 256–262
Bandyopadhyay T, Chatterjee R, Chung D, Swaminanithan M, and Tummala R (2009) Electrical modeling of through silicon and package vias, IEEE Inter. Conf. 3D System Integration, Sep, pp 28–30
Sentaurus Device User Guide (2008) Version A-2008.09, Synopsis Inc., Mountain View, CA
Katti G, Stucchi M, Olmen JV, Meyer KD, and Dehaene W (2010) Through-silicon-via capacitance reduction technique to benefit 3-D IC performance, IEEE Electron Device Lett., vol. 31, no. 4, Jun, pp 549–551
Kikuchi H et al (2008) Tungsten through-silicon via technology for three-dimensional LSIs. Jpn J Appl Phys 47(4):2801–2806
Pucel R (1985) Gallium arsenide technology, Technology and Design Considerations of Monolithic Microwave Integrated Circuits. In: Ferry D (ed) Howard W. Sams and Co., Indianapolis, IN, chapter 6, pp 216
Young B (2001) Digital signal integrity. Prentice Hall, New York, pp 45
Marchal P et al (2009) 3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot, Proceedings of the IEEE, Volume: 97, Issue: 1, pp 96–107
Katti G et al (2009) 3D Stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective Bonding, in IEDM Tech. Dig., pp 357–360
Rabaey J et al (2003) Digital integrated circuits, Upper Saddle River, New Jersey 07458, 2nd edn. Prentice Hall Electronics and VLSI Series
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Stucchi, M., Katti, G., Velenis, D. (2011). TSV Characterization and Modeling. In: Papanikolaou, A., Soudris, D., Radojcic, R. (eds) Three Dimensional System Integration. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0962-6_3
Download citation
DOI: https://doi.org/10.1007/978-1-4419-0962-6_3
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-0961-9
Online ISBN: 978-1-4419-0962-6
eBook Packages: EngineeringEngineering (R0)