Abstract
The on-chip bus is the backbone of any SoC, and it is a means to efficiently connect various components including processors, memory, and peripherals. The challenges for an on-chip bus are not minor: it has to accommodate a wide range of communication needs with a single, unified architecture. In this chapter we review the key characteristics of the on-chip bus, using several existing on-chip bus standards as examples: ARM/AMBA, IBM/Coreconnect, and Wishbone. We also look at some of the long-term challenges for on-chip interconnect, and how this will affect the design of hardware–software interfaces.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
IBM (2009) Coreconnect bus architecture. Tech. rep., https://www-01.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect\_Bus\_Architecture
Micheli GD, Benini L (2006) Networks on Chips: Technology and Tools (Systems on Silicon). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA
Pasricha S, Dutt N (2008) On-Chip Communication Architectures: System on Chip Interconnect. Morgan Kaufmann
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Schaumont, P.R. (2010). On-Chip Busses. In: A Practical Introduction to Hardware/Software Codesign. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6000-9_8
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6000-9_8
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5999-7
Online ISBN: 978-1-4419-6000-9
eBook Packages: EngineeringEngineering (R0)