Abstract
The end of the ITRS roadmap for classical CMOS devices and circuits envisions the emergence of future nanotechnologies and nanodevices and also evidences many new related challenges. This chapter covers some of these issues using a tutorial presentation style.
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References
(2007) International technology roadmap for semiconductors. [Online]. Available: http://www.itrs.net/Links/2007ITRS/Home2007.htm
K. K. Likharev, “Single-electron devices and their applications,” Proceedings of the IEEE, vol. 87, no. 4, pp. 606–632, April 1999.
U. Feldkamp and C. M. Niemeyer, “Rational design of DNA nanoarchitectures,” Angewandte Chemie International Edition, vol. 45, pp. 1856–1876, 2006.
C. Lin, Y. Liu, S. Rinker, and H. Yan, “DNA tile based self-assembly: Building complex nanoarchitectures,” Chemical Physics and Physical Chemistry, vol. 7, no. 8, pp. 1641–1647, 2006.
J. E. Green, J. W. Choi, A. Boukai, Y. Bunimovich, E. Johnston-Halperin, E. DeIonno, Y. Luo, B. A. Sheriff, K. Xu, Y. S. Shin, H.-R. Tseng, J. F. Stoddart, and J. R. Heath, “A 160-kilobit molecular electronic memory patterned at \(10^{11}\) bits per square centimeter,” Nature, vol. 445, pp. 414–417, 2007.
S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu, “Nano, quantum, and molecular computing: Are we ready for the validation and test challenges?” in Proceedings of the 8th IEEE International High-Level Design Validation and Test Workshop, 2003, pp. 3–7.
S. Lazarova-Molnar, V. Beiu, and W. Ibrahim, “Reliability the fourth optimization pillar of nanoelectronics,” in Proceedings IEEE International Conference on Signal Processing and Communications (ICSPC), 24–27 Nov. 2007, pp. 73–76.
V. Beiu, W. Ibrahim, and S. Lazarova-Molnar, “A fresh look at majority multiplexing when devices get into the picture,” in Proceedings of the 7th IEEE Conference on Nanotechnology (IEEE-NANO), 2–5 Aug. 2007, pp. 883–888.
V. Beiu, “Grand challenges of nanoelectronics and possible architectural solutions: What do Shannon, von Neumann, Kolmogorov, and Feynman have to do with Moore,” in Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL), 13–16 May 2007, p. 1–6.
J. A. Hutchby, G. I. Bourianoff, V. V. Zhirnov, and J. E. Brewer, “Extending the road beyond CMOS,” IEEE Circuits and Devices Magazine, vol. 18, no. 2, pp. 28–41, 2002.
R. H. Chen, A. N. Korotkov, and K. K. Likharev, “Single-electron transistor logic,” Applied Physics Letters, vol. 68, pp. 1954–1956, 1996.
C. P. Heij, P. Hadley, and J. E. Mooij, “Single-electron inverter,” Applied Physics Letters, vol. 78, pp. 1140–1142, 2001.
K. Uchida, J. Koga, R. Ohba, and A. Toriumi, “Programmable single-electron transistor logic for future low-power intelligent LSI: Proposal and room-temperature operation,” IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1623–1630, July 2003.
Y. Takahashi, A. Fujiwara, Y. Ono, and K. Murase, “Silicon single-electron devices and their applications,” in Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL), 23–25 May 2000, pp. 411–420.
Z. A. K. Durrani, A. C. Lnine, and H. Ahmed, “Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells,” IEEE Transactions on Electron Devices, vol. 47, no. 12, pp. 2334–2339, Dec. 2000.
N. J. Stone, H. Ahmed, and K. Nakazato, “A high-speed silicon single-electron random access memory,” IEEE Electron Device Letters, vol. 20, no. 11, pp. 583–585, Nov. 1999.
J. Han and P. Jonker, “A system architecture solution for unreliable nanoelectronic devices,” IEEE Transactions on Nanotechnology, vol. 1, no. 4, pp. 201–208, Dec. 2002.
(2000, Nov.) Technology roadmap for nanoelectronics. Microelectronics Advanced Research Initiative - MELARI NANO. [Online]. Available: http://www.itrs.net/links/2001itrs/Links/modeling/Nano2000 WEB Version.pdf
P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, and G. I. Haddad, “Digital circuit applications of resonant tunneling devices,” Proceedings of the IEEE, vol. 86, no. 4, pp. 664–686, April 1998.
J. P. A. van der Wagt, A. C. Seabaugh, and I. Beam, E. A., “RTD/HFET low standby power SRAM gain cell,” IEEE Electron Device Letters, vol. 19, no. 1, pp. 7–9, Jan. 1998.
M. A. Reed, W. R. Frensley, R. J. Matyi, J. N. Randall, and A. C. Seabaugh, “Realization of a three-terminal resonant tunneling device: The bipolar quantum resonant tunneling transistor,” Applied Physics Letters, vol. 54, pp. 1034–1036,, 1989.
J. Stock, J. Malindretos, K. M. Indlekofer, M. Pottgens, A. Forster, and H. Luth, “A vertical resonant tunneling transistor for application in digital logic circuits,” IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1028–1032, June 2001.
V. V. Zhirnov, J. A. Hutchby, G. I. Bourianoffls, and J. E. Brewer, “Emerging research logic devices,” IEEE Circuits and Devices Magazine, vol. 21, no. 3, pp. 37–46, 2005.
E. F. Codd, Cellular Automata. London: Academic Press, 1968.
C. S. Lent and P. D. Tougaw, “A device architecture for computing with quantum dots,” Proceedings of the IEEE, vol. 85, no. 4, pp. 541–557, April 1997.
G. Bourianoff, “The future of nanocomputing,” Computer, vol. 36, no. 8, pp. 44–53, Aug. 2003.
A. O. Orlov, I. Amlani, R. Kummamuru, R. Ramasubramaniam, G. Toth, C. S. Lent, G. H. Bernstein, and G. L. Snider, “Experimental demonstration of clocked single-electron switching in quantum-dot cellular automata,” Applied Physics Letters, vol. 77, pp. 295–297, 2000.
A. O. Orlov, R. Kummamuru, R. Ramasubramaniam, G. Toth, C. S. Lent, G. H. Bernstein, and G. L. Snider, “Experimental demonstration of a latch in clocked quantum-dot cellular automata,” Applied Physics Letters, vol. 78, pp. 1625–1627, 2001.
A. O. Orlov, R. Kummamuru, R. Ramasubramaniam, G. Toth, C. S. Lent, G. H. Bernstein, and G. L. Snider, “Clocked quantum-dot cellular automata shift register,” Surface Science, vol. 532, pp. 1193–1198, 2003.
P. D. Tougaw and C. S. Lent, “Dynamic behavior of quantum cellular automata,” Journal of Applied Physics, vol. 80, pp. 4722–4736, 1996.
C. S. Lent, B. Isaksen, and M. Lieberman, “Molecular quantum-dot cellular automata,” Journal of American Chemical Society, vol. 125, pp. 1056–1063, 2003.
K. Nikolic, D. Berzon, and M. Forshaw, “Relative performance of three nanoscale devices - CMOS, RTDs and QCAs - against a standard computing task,” Nanotechnology, vol. 12, no. 1, pp. 38–43, 2001.
R. P. Cowburn and M. E. Welland, “Room temperature magnetic quantum cellular automata,” Science, vol. 287, no. 5457, pp. 1466–1468, 2000.
D. A. Allwood, G. Xiong, M. D. Cooke, C. C. Faulkner, D. Atkinson, N. Vernier, and R. P. Cowburn, “Submicrometer ferromagnetic NOT gate and shift register,” Science, vol. 296, pp. 2003–2006, 2002.
K. B. K. Teo, R. G. Lacerda, M. H. Yang, A. S. Teh, L. A. W. Robinson, S. H. Dalal, N. L. Rupesinghe, M. Chhowalla, S. B. Lee, D. A. Jefferson, D. G. Hasko, G. A. J. Amaratunga, W. L. Milne, P. Legagneux, L. Gangloff, E. Minoux, J. P. Schnell, and D. Pribat, “Carbon nanotube technology for solid state and vacuum electronics,” IEE Proceedings -Circuits, Devices and Systems, vol. 151, no. 5, pp. 443–451, 2004.
S. J. Tans, A. R. M. Verschueren, and C. Dekker, “Room-temperature transistor based on a single carbon nanotube,” Nature, vol. 393, pp. 49–52, 1998.
H. W. C. Postma, T. F. Teepen, Z. Yao, M. Grifoni, and C. Dekker, “Carbon nanotubes single-electron transistors at room temperature,” Science, vol. 293, pp. 76–79, 2001.
A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, “Logic circuits with carbon nanotube transistors,” Science, vol. 294, pp. 1317–1320, 2001.
A. Javey, Q. Wang, A. Urai, Y. Li, and H. Dai, “Carbon nanotube transistor arrays for multi-stage complementary logic and ring oscillators,” Nano Letters, vol. 2, pp. 929–932, 2002.
Y. Huang, X. F. Duan, Q. Wei, and C. M. Lieber, “Directed assembly of one-dimensional nanostructures into functional networks,” Science, vol. 291, pp. 630–633, 2001.
N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff, and J. R. Heath, “Ultrahigh-density nanowire lattices and circuits,” Science, vol. 300, pp. 112–115, 2003.
X. F. Duan, Y. Huang, Y. Cui, J. F. Wang, and C. M. Lieber, “Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices,” Nature, vol. 409, no. 6816, pp. 66–69, 2001.
Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K. Kim, and C. M. Lieber, “Logic gates and computation from assembled nanowire building blocks,” Science, vol. 294, pp. 1313–1317, 2001.
Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath, and C. M. Lieber, “Nanowire crossbar arrays as address decoders for integrated nanosystems,” Science, vol. 302, pp. 1377–1379, 2003.
C. Joachim, J. K. Gimzewski, and A. Aviram, “Electronics using hybrid-molecular and mono-molecular devices,” Nature, vol. 408, pp. 541–548, 2000.
H. Park, J. Park, A. K. L. Lim, E. H. Anderson, A. P. Alivisatos, and P. L. McEuen, “Nanomechanical oscillations in a single-C-60 transistor,” Nature, vol. 407, pp. 57–60, 2000.
Y. Luo, C. P. Collier, J. O. Jeppesen, K. A. Nielsen, E. Delonno, G. Ho, J. Perkins, H. R. Tseng, T. Yamamoto, J. F. Stoddart, and J. R. Heath, “Two-dimensional molecular electronics circuits,” Chemical Physics and Physical Chemistry, vol. 3, no. 6, pp. 519–525, 2002.
M. R. Stan, P. D. Franzon, S. C. Goldstein, J. C. Lach, and M. M. Ziegler, “Molecular electronics: From devices and interconnect to circuits and architecture,” Proceedings of the IEEE, vol. 91, no. 11, pp. 1940–1957, 2003.
X. Ma, D. B. Strukov, J. H. Lee, and K. K. Likharev, “Afterlife for silicon: Cmol circuit architectures,” in Proceedings of the 5th IEEE Conference Nanotechnology, 2005, pp. 175–178.
P. Bunyk, K. Likharev, and D. Zinoviev, “RSFQ technology: Physics and devices,” International Journal of High Speed Electronics and Systems, vol. 11, no. 1, pp. 257–305, 2001.
W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens, and K. K. Likharev, “Rapid single flux quantum T-flip flop operating up to 770 GHz,” IEEE Transactions on Applied Superconductivity, vol. 9, no. 2, pp. 3212–3215, 1999.
D. K. Brock, “RSFQ technology: Circuits and systems,” International Journal of High Speed Electronics, vol. 11, no. 1, pp. 307–362, 2001.
A. M. Kadin, C. A. Mancini, M. J. Feldman, and D. K. Brock, “Can RSFQ logic circuits be scaled to deep submicron junctions?” IEEE Transactions on Applied Superconductivity, vol. 11, no. 1, pp. 1050–1055, 2001.
D. K. Brock, E. K. Track, and J. M. Rowell, “Superconductor ICs: The 100-GHz second generation,” IEEE Spectrum, vol. 37, no. 12, pp. 40–46, 2000.
J. E. Mooij, T. P. Orlando, L. Levitov, L. Tian, C. H. van der Wal, and S. Lloyd, “Josephson persistent-current qubit,” Science, vol. 285, pp. 1036–1039, 1999.
I. Chiorescu, Y. Nakamura, C. J. P. M. Harmans, and J. E. Mooij, “Coherent quantum dynamics of a superconducting flux qubit,” Science, vol. 299, pp. 1869–1871, 2003.
P. Jonker and J. Han, “On quantum and classical computing with arrays of superconducting persistent current qubits,” in Proceedings of the 5th IEEE International Workshop on Computer Architectures for Machine Perception, 2000, pp. 69–78.
J. Han and P. Jonker, “Novel computing architecture on arrays of Josephson persistent current bits,” in Proceedings of the 5thth International Conference on Modeling and Simulation of Microsystems (MSM), San Juan, Puerto Rico, USA, April 2002, pp. 636–639.
M. Johnson, “The all-metal spin transistor,” IEEE Spectrum, vol. 31, no. 5, pp. 47–51, 1994.
C. L. Dennis, C. V. Tiusan, J. F. Gregg, G. J. Ensell, and S. M. Thompson, “Silicon spin diffusion transistor: Materials, physics and device characteristics,” IEE Proceedings -Circuits, Devices and Systems, vol. 152, no. 4, pp. 340–354, 2005.
M. Johnson, “Magnetoelectronic memories last and last,” IEEE Spectrum, vol. 37, no. 2, pp. 33–40, 2000.
C. K. Lo, Y. W. Huang, Y. D. Yao, D. R. Huang, and J. H. Huang, “Spin transistor for magnetic recording,” IEEE Transactions on Magnetics, vol. 41, no. 2, pp. 892–895, 2005.
M. Tanaka and S. Sugahara, “MOS-based spin devices for reconfigurable logic,” IEEE Transactions on Electron Devices, vol. 54, no. 5, pp. 961–976, 2007.
M. Forshaw, D. Crawley, P. Jonker, J. Han, and C. S. Torres, “Nano Arch review: A review of the status of research and training into architectures for nanoelectronic and nanophotonic systems in the European research area,” FP6/2002/IST/1 (Ext. rep. 507519). London: University College London., Technical Report, 2004.
V. Beiu, S. Aunet, J. Nyathi, R. R. Rydberg, and W. Ibrahim, “Serial addition: Locally connected architectures,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2564–2579, Nov. 2007.
M. Hartmann and P. C. Haddow, “Evolution of fault-tolerant and noise-robust digital designs,” IEE Proceedings -Computers and Digital Techniques, vol. 151, no. 4, pp. 287–294, 2004.
M. Forshaw, R. Stadler, D. Crawley, and K. Nicolic, “A short review of nanoelectronic architectures,” Nanotechnology, vol. 15, pp. S220–S223, 2004.
S. Lazarova-Molnar, V. Beiu, and W. Ibrahim, “A strategy for reliability assessment of future nano-circuits,” in Proceedings of the 11th WSEAS International Conference on Circuits (ICC). Stevens Point, WI: World Scientific and Engineering Academy and Society (WSEAS), 2007, pp. 60–65.
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Stanisavljević, M., Schmid, A., Leblebici, Y. (2011). Nanotechnology and Nanodevices. In: Reliability of Nanoscale Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6217-1_3
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