Skip to main content
SpringerLink
Log in

Introduction

  • Chapter
  • First Online:
On-Chip Interconnect with aelite

Part of the book series: Embedded Systems ((EMSY))

  • 576 Accesses

Abstract

Embedded systems are rapidly growing in numbers and importance as we crowd our living rooms with digital televisions, game consoles and set-top boxes and our pockets (or maybe handbags) with mobile phones, digital cameras and personal digital assistants. Even traditional PC and IT companies are making an effort to enter the consumer-electronics business [5] with a mobile phone market that is four times larger than the PC market (1.12 billion compared to 271 million PCs and laptops in 2007) [177].

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    The names are merely used to distinguish the three processors. Their actual architecture is of no relevance for the example. The three processor families have, however, been demonstrated together with the interconnect proposed in this work.

  2. 2.

    For brevity, we assume that the processors have local instruction memories and leave out the loading of these memories. In Chapter 7 we demonstrate how loading of instructions is taken into account.

  3. 3.

    We return to discuss other aspects of composability in Chapter 9, when reviewing related work.

  4. 4.

    Sharing of processors between applications is outside the scope of this work, a reasonable limitation that is elaborated on in Chapter 7 when discussing our example system.

  5. 5.

    More (accurate) information is available, but with smaller scope (local). Run-time processing is also usually (much) more constrained than design-time processing in terms of compute power.

References

  1. AHBLite (2001) Multi-Layer AHB, AHB-Lite Product Information. ARM Limited, San Jose, CA

    Google Scholar 

  2. Altera (2008) Avalon Interface Specifications. Altera Corporation, San Jose, CA. Available on www.altera.com

    Google Scholar 

  3. Anderson MR (2004) When companies collide: the convergence to consumer electronics. Strategic News Service, Friday Harbor, WA

    Google Scholar 

  4. ARINC653 (1997) ARINC Specification 653. Avionics Application Software Standard Interface

    Google Scholar 

  5. AXI (2003) AMBA AXI Protocol Specification. ARM Limited, San Jose, CA

    Google Scholar 

  6. Azimi M, Cherukuri N, Jayashima D, Kumar A, Kundu P, Park S, Schoinas I, Vaidya A (2007) Integration challenges and tradeoffs for tera-scale architectures. Intel Technology Journal 11(3):173–184

    Article  Google Scholar 

  7. Beigne E, Clermidy F, Vivet P, Clouard A, Renaudin M (2005) An asynchronous NOC architecture providing low latency service and its multi-level design framework. In: Proc. ASYNC

    Google Scholar 

  8. Bekooij M, Moreira O, Poplavko P, Mesman B, Pastrnak M, van Meerbergen J (2004) Predictable embedded multiprocessor system design. LNCS 3199:77–91

    Google Scholar 

  9. Benini L, de Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Computer 35(1):70–80

    Article  Google Scholar 

  10. van Berkel K (2009) Multi-core for mobile phones. In: Proc. DATE

    Google Scholar 

  11. Bjerregaard T, Sparsø J (2005) A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. In: Proc. ASYNC

    Google Scholar 

  12. Bjerregaard T, Mahadevan S, Grøndahl Olsen R, Sparsø J (2005) An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip. In: Proc. SOC

    Google Scholar 

  13. Bjerregaard T, Stensgaard M, Sparsø J (2007) A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. In: Proc. DATE

    Google Scholar 

  14. Buttazo GC (1977) Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Kluwer Publishers, Dordrecth

    Google Scholar 

  15. Carloni L, McMillan K, Sangiovanni-Vincentelli A (2001) Theory of latency-insensitive design. IEEE Transactions on CAD of Integrated Circuits and Systems 20(9):1059–1076

    Article  Google Scholar 

  16. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proc. DAC

    Google Scholar 

  17. Dielissen J, Rădulescu A, Goossens K, Rijpkema E (2003) Concepts and implementation of the Philips network-on-chip. In: IP-Based SOC Design

    Google Scholar 

  18. DTL (2002) Device Transaction Level (DTL) Protocol Specification. Version 2.2. Philips Semiconductors, Washington, DC

    Google Scholar 

  19. Dutta S, Jensen R, Rieckmann A (2001) Viper: a multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers 18(5):21–31

    Article  Google Scholar 

  20. Ernst D (2004) Limits to modularity: a review of the literature and evidence from chip design. Economics Study Area Working Papers 71, East-West Center, Honolulu, HI

    Google Scholar 

  21. FSL (2007) Fast Simplex Link (FSL) Bus v2.11a. Xilinx, Inc, San Jose, CA

    Google Scholar 

  22. Gal-On S (2008) Multicore benchmarks help match programming to processor architecture. In: MultiCore Expo

    Google Scholar 

  23. Goossens K, Dielissen J, Gangwal OP, González Pestana S, Rădulescu A, Rijpkema E (2005) A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In: Proc. DATE

    Google Scholar 

  24. Goossens K, Dielissen J, Rădulescu A (2005) The Æthereal network on chip: concepts, architectures, and implementations. IEEE Design and Test of Computers 22(5):21–31

    Google Scholar 

  25. Graham R (1969) Bounds on multiprocessing timing anomalies. SIAM Journal of Applied Mathematics 17(2):416–429

    Article  MATH  Google Scholar 

  26. Hansson A, Goossens K (2007) Trade-offs in the configuration of a network on chip for multiple use-cases. In: Proc. NOCS

    Google Scholar 

  27. Hansson A, Goossens K (2009) An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. In: Proc. CODES+ISSS

    Google Scholar 

  28. Hansson A, Coenen M, Goossens K (2007) Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. In: Proc. CODES+ISSS

    Google Scholar 

  29. Hansson A, Coenen M, Goossens K (2007) Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. In: Proc. DATE

    Google Scholar 

  30. Hansson A, Goossens K, Rădulescu A (2007) A unified approach to mapping and routing on a network on chip for both best-effort and guaranteed service traffic. VLSI Design 2007:1–16

    Google Scholar 

  31. Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2008) Applying dataflow analysis to dimension buffers for guaranteed performance in Networks on Chip. In: Proc. NOCS

    Google Scholar 

  32. Hansson A, Goossens K, Bekooij M, Huisken J (2009) Compsoc: a template for composable and predictable multi-processor system on chips. ACM Transactions on Design Automation of Electronic Systems 14(1):1–24

    Article  Google Scholar 

  33. Hansson A, Subburaman M, Goossens K (2009) Aelite: a flit-synchronous network on chip with composable and predictable services. In: Proc. DATE

    Google Scholar 

  34. Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2009) Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Computers and Design Techniques

    Google Scholar 

  35. Henkel J (2003) Closing the SoC design gap. Computer 36(9):119–121

    Article  Google Scholar 

  36. Ilitzky DA, Hoffman JD, Chun A, Esparza BP (2007) Architecture of the scalable communications core’s network on chip. IEEE Micro 27(5):62–74

    Article  Google Scholar 

  37. ITRS (2007) International technology roadmap for semiconductors. System Drivers

    Google Scholar 

  38. ITRS (2007) International technology roadmap for semiconductors. Design

    Google Scholar 

  39. Jantsch A (2006) Models of computation for networks on chip. In: Proc. ACSD

    Google Scholar 

  40. Keutzer K, Malik S, Newton AR, Rabaey JM, Sangiovanni-Vincentelli A (2000) System-level design: orthogonalization of concerns and platform-based design. IEEE Transactions on CAD of Integrated Circuits and Systems 19(12):1523–1543

    Article  Google Scholar 

  41. Kopetz H, El Salloum C, Huber B, Obermaisser R, Paukovits C (2008) Composability in the time-triggered system-on-chip architecture. In: Proc. SOCC

    Google Scholar 

  42. Kramer J, Magee J (1990) The evolving philosophers problem: dynamic change management. IEEE Transactions on Software Engineering 16(11):1293–1306, http://10.1109/32.60317

    Article  Google Scholar 

  43. Krstić M, Grass E, Gürkaynak F, Vivet P (2007) Globally asynchronous, locally synchronous circuits: overview and outlook. IEEE Design and Test of Computers 24(5):430–441

    Article  Google Scholar 

  44. Lickly B, Liu I, Kim S, D Patel H, Edwards SA, Lee EA (2008) Predictable programming on a precision timed architecture. In: Proc. CASES

    Google Scholar 

  45. Lu Z, Haukilahti R (2003) NOC application programming interfaces: high level communication primitives and operating system services for power management. In: Networks on Chip, Kluwer Academic Publishers, Dordrecht

    Google Scholar 

  46. Magarshack P, Paulin PG (2003) System-on-chip beyond the nanometer wall. In: Proc. DAC

    Google Scholar 

  47. Marescaux T, Mignolet J, Bartic A, Moffat W, Verkest D, Vernalde S, Lauwereins R (2003) Networks on chip as hardware components of an OS for reconfigurable systems. In: Proc. FPL

    Google Scholar 

  48. Martin G (2006) Overview of the MPSoC design challenge. In: Proc. DAC

    Google Scholar 

  49. Moreira O, Valente F, Bekooij M (2007) Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor. In: Proc. EMSOFT

    Google Scholar 

  50. Murali S, Coenen M, Rădulescu A, Goossens K, De Micheli G (2006) A methodology for mapping multiple use-cases on to networks on chip. In: Proc. DATE

    Google Scholar 

  51. Muttersbach J, Villiger T, Fichtner W (2000) Practical design of globally-asynchronous locally-synchronous systems. In: Proc. ASYNC

    Google Scholar 

  52. Nachtergaele L, Catthoor F, Balasa F, Franssen F, De Greef E, Samsom H, De Man H (1995) Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems. In: Proc. MTDT

    Google Scholar 

  53. Nachtergaele L, Moolenaar D, Vanhoof B, Catthoor F, De Man H (1998) System-level power optimization of video codecs on embedded cores: a systematic approach. Journal of VLSI Signal Processing 18(12):89–109

    Google Scholar 

  54. Nesbit K, Moreto M, Cazorla F, Ramirez A, Valero M, Smith J (2008) Multicore resource management. IEEE Micro 28(3):6–16

    Article  Google Scholar 

  55. Nieuwland A, Kang J, Gangwal O, Sethuraman R, Busá N, Goossens K, Peset Llopis R, Lippens P (2002) C-HEAP: a heterogeneous multi-processor architecture template and scalable and flexible protocol for the design of embedded signal processing systems. Design Automation for Embedded Systems 7(3):233–270

    Article  MATH  Google Scholar 

  56. Obermaisser R (2007) Integrating automotive applications using overlay networks on top of a time-triggered protocol. LNCS 4888:187–206

    Google Scholar 

  57. OCP (2007) OCP Specification 2.2. OCP International Partnership

    Google Scholar 

  58. Owens J, Dally W, Ho R, Jayasimha D, Keckler S, Peh LS (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27(5):96–108

    Article  Google Scholar 

  59. Panades I, Greiner A, Sheibanyrad A (2006) A low cost network-on-chip with guaranteed service well suited to the GALS approach. In: Proc. NANONET

    Google Scholar 

  60. Paukovits C (2008) The time-triggered system-on-chip architecture. PhD thesis, Technische Universität Wien, Institut für Technische Informatik

    Google Scholar 

  61. PLB (2003) Processor Local Bus (PLB) v3.4. Xilinx Inc, San Jose, CA

    Google Scholar 

  62. Poplavko P, Basten T, Bekooij M, van Meerbergen J, Mesman B (2003) Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. In: Proc. CASES

    Google Scholar 

  63. Pullini A, Angiolini F, Murali S, Atienza D, De Micheli G, Benini L (2007) Bringing NoCs to 65 nm. IEEE Micro 27(5):75–85

    Article  Google Scholar 

  64. Rostislav D, Vishnyakov V, Friedman E, Ginosar R (2005) An asynchronous router for multiple service levels networks on chip. In: Proc. ASYNC

    Google Scholar 

  65. Rowen C, Leibson S (2004) Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors. Prentice Hall PTR, Upper Saddle River, NJ

    Google Scholar 

  66. Rumpler B (2006) Complexity management for composable real-time systems. In: Proc. ISORC

    Google Scholar 

  67. Sasaki H (1996) Multimedia complex on a chip. In: Proc. ISSCC

    Google Scholar 

  68. Sgroi M, Sheets M, Mihal A, Keutzer K, Malik S, Rabaey J, Sangiovanni-Vincentelli A (2001) Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proc. DAC

    Google Scholar 

  69. Smith B (2008) ARM and Intel battle over the mobile chip’s future. Computer 41(5):15–18

    Article  Google Scholar 

  70. Soudris D, Zervas ND, Argyriou A, Dasygenis M, Tatas K, Goutis C, Thanailakis A (2000) Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications. In: Proc. PATMOS

    Google Scholar 

  71. TechInsights (2008) Embedded Market Study, TechInsights, Ottawa ON

    Google Scholar 

  72. Wingard D (2004) Socket-based design using decoupled interconnects. In: Interconnect-Centric design for SoC and NoC, Kluwer, Dordrecht

    Google Scholar 

  73. Zhang H (1995) Service disciplines for guaranteed performance service in packet-switching networks. Proceedings of the IEEE 83(10):1374–1396

    Article  Google Scholar 

  74. Hansson A, Goossens K, Rădulescu A (2005) A unified approach to constrained mapping and routing on network-on-chip architectures. In: Proc. CODES+ISSS

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Research & Development ARM Ltd., Cambridge, UK

    Andreas Hansson

  2. Eindhoven University of Technology, Eindhoven, The Netherlands

    Kees Goossens

Authors
  1. Andreas Hansson
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kees Goossens
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Andreas Hansson .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Hansson, A., Goossens, K. (2011). Introduction. In: On-Chip Interconnect with aelite. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6865-4_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-6865-4_1

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-6496-0

  • Online ISBN: 978-1-4419-6865-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation