Abstract
In the previous chapter, we introduced our work and in this chapter, we continue by laying the foundation for our research. There are several design aspects affecting power distribution and we begin by describing the design problem traits characteristic of the analog portion of analog or mixed-signal ASICs. Then, we discuss and illustrate the commonly used physical design styles in these ASICs. Next, we describe key design concerns associated with analog power distribution and highlight previous synthesis methods used to automate part of this design task. We complete this chapter by evaluating how well the previous synthesis methods support design styles and address the critical physical design and electrical issues.
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References
T. Schmerbeck, R. Richetta, and L. Smith, “A 27MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection”, In Proceedings IEEE International Solid-State Circuits Conference, pp. 136–137 & 304, February 1991.
R. Philpott, R. Kertis, R. Richetta, T. Schmerbeck, and D. Schulte, “A 7MB/Sec(65MHZ), Mixed-Signal, Magnetic Recording Channel DSP Using Partial Response Signaling with Maximum Likelihood Detection”, In Proceedings IEEE Custom Integrated Circuits Conference, pp. 10.4.1–10.4.4, May 1993.
J. A. Olmstead, S. Vulih, “Noise Problems in Mixed Analog-Digital Integrated Circuits”, In Proceedings IEEE Custom Integrated Circuits Conference, pp. 659–662, April 1987.
R. van de Grift, “Design Methodology for mixed signal IC’s, Philips Electronic Design & Tools, the Netherlands”, presented at Carnegie-Mellon University, February 27, 1992.
S. Chowdhury, “An Automated Design of Minimum-Area IC Power/Ground Nets”, In Proceedings 24th Design Automation Conference, pp. 223–229, June 1987.
R. Colwell, “What Ground Bounce Did To Multiflow”, Intel Technical Memorandum, September 1991.
G. A. Katopis, “Delta-I Noise Specification for a High-Performance Computing Machine”, In Proceedings of the IEEE, Vol. 73, No. 9, pp. 1405–1415, September 1985.
M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching Properties of MOS Transistors”, IEEE Journal of Solid-State Circuits, Vol. SC-24, No. 5, pp. 1433–1440, October 1987.
J. Cohn, D. Garrod, R. Rutenbar, and L. Carley, “KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 3, pp. 330–342, March 1991.
B. Basaran, R. A. Rutenbar, L. R. Carley, “Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 418–421, November 1993.
D. Jepsen and C. Gelatt Jr., “Macro Placement by Monte Carlo Annealing”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 495–498, November 1984.
R. Otten and L. van Ginneken, “Floorplan Design using Simulated Annealing”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 96–98, November 1984.
H-J. Rothermel and D. A. Mlynski, “Computation of Power Supply Nets in VLSI Layout”, In Proceedings 18th Design Automation Conference, pp. 37–42, June 1981.
R. Y. Tsui, “A Power Bus Channel Router”, In Proceedings IEEE Custom Integrated Circuits Conference, pp. 11.6.1–11.6.4, April 1988.
Z. A. Syed, A. El Gamal, M. A. Breuer, “On Routing for Custom Integrated Circuits”, In Proceedings 19th Design Automation Conference, pp. 887–893, June 1982.
B. Preas and M. Lorenzetti, Physical Design Automation of VLSI Systems, in Chapter 4, “Placement, Assignment and Floorplanning”, pp. 94 – 97, Benjamin/Cummings Publishing Co., Menlo Park, CA, 1988.
S. Mitra, S. Nag, R. Rutenbar, and L. Carley, “System-level Routing of Mixed-Signal ASICs in WREN”, In Proceedings IEEE International Conference on Computer-Aided Design, pp. 394–399, November 1992.
A. Dunlop, G. Gross, C. Kimble, et al., “Features in LTX2 for Array Layout”, in Proceedings of International Symposium on Circuits and Systems, pp. 21–23, 1985.
C. Kimble, et al., “Analog Autorouted VLSI”, in Proceedings Custom Integrated Circuits Conference, pp. 72078, June 1985.
L. D. Smith, et al., “A CMOS-Based Analog Standard Cell Product Family”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, pp. 370–379, April 1989.
C. A. Laber, “Design Considerations for a High-Performance 3-μm CMOS Analog Standard-Cell Library”, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 2, pp. 181–189, April 1987.
N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, in Chapter 9, “Controlling Substrate Coupling in Heavily-Doped Bulk Processes”, pp. 183–216, Kluwer Academic Publishers, Boston MA, 1995.
T. Mitsuhashi and E. Kuh, “Power and Ground Network Topology Optimization for Cell Based VLSIs”, In Proceedings 29th Design Automation Conference, pp. 524–529, June 1992.
M. Depey, et al., “A 1 OK-Gate 950-MHz CML Demonstrator Circuit Made with a 1-μm Trench-Isolated Bipolar Silicon Technology”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, pp. 552–557, June 1989.
W. Fang, “Accurate Analytical Delay Expressions for ECL and CML Circuits and Their Applications to Optimizing High-Speed Bipolar Circuits”, IEEE Journal of Solid-State Circuits, Vol 25, No. 2, pp. 572–583, April 1990.
M. Kokado, et al., “A 54,000-Gate ECL Array with Substrate Power Supply”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, pp. 1271–1274, October 1989.
E. Vittoz, “The design of High-Performance Analog Circuits on Digital CMOS Chips”, IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 3, pp. 657–665, June
R. J. Widlar, “Controlling Substrate Currents in Junction-Isolated IC’s”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, pp. 1090–1097, August 1987.
H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, in Chapter 7, “Crosstalk and Power Distribution Noise”, pp. 281–337, Addison-Wesley Publishing Co., Reading MA, 1990.
J. Trnka, R. Hedman, G. Koehler, and K. Ladin, “A Device Level Auto Place and Wire Methodology for Analog and Digital Masterslices”, In Proceedings IEEE International Solid-State Circuits Conference, pp. 262–263, February, 1988.
Z. A. Syed and A. El Gamal, “Single Layer Routing of Power and Ground Networks in Integrated Circuits”, pp. 53–63, Journal of Digital Systems, Feb. 1982.
C. Lursinsap, “Power Routing in Floorplan Layouts”, Integration, the VLSI Journal, Vol. 8, pp. 249–268, 1989.
S. Chowdbury and M. A. Breuer, “The Construction of Minimal Area Power and Ground Nets for VLSI Circuits”, In Proceedings 22nd Design Automation Conference, pp. 794–797, June 1985.
S. Chowdhury and M. A. Breuer, “Minimal Area Sizing of Power and Ground Nets for VLSI Circuits”, In Proceedings 4th MIT Conference on Advanced Research in VLSI, pp. 141–169, April, 1986.
R. Kolla, “A Dynamic Programming Approach to the Power Supply Net Sizing Problem”, In Proceedings European Design Automation Conference, pp. 600–604, March 1990.
A. S. Moulton, “Laying the Power and Ground Wires on a VLSI Chip”, In Proceedings 20th Design Automation Conference, pp. 754–755, June 1983.
K. Buttle et al., “A Multirate Transceiver IC for Four-Wire Full Duplex Data Transmission”, In Proceedings IEEE International Solid-State Circuits Conference, pp. 234 – 236 & 319, February 1991.
T. Schmerbeck, “Design Strategies for Reducing the Effects of Noise Coupling in Analog and Mixed-Mode ICs”, in presentation for course on Practical Aspects of Analog and Mixed-Mode IC Design, Beaverton Oregon, May 18, 1993.
N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, in Chapter 8, “Modeling Chip/Package Power Distribution”, pp. 149–182, Kluwer Academic Publishers, Boston MA, 1995.
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Stanisic, B.R., Rutenbar, R.A., Carley, L.R. (1996). Power Distribution Noise and Physical Design Methods. In: Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1399-1_2
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DOI: https://doi.org/10.1007/978-1-4613-1399-1_2
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