Abstract
Scheduling assigns operators in the behavioral specification to control steps that represent clock cycles in the completed design. Because scheduling and other design tasks are heavily interdependent, it has been recognized as an important part of the synthesis problem [Gajski86]. When interface information is added to the synthesis problem, scheduling becomes even more important because it determines whether timing constraints can be met in the resulting implementation.
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© 1990 Kluwer Academic Publishers
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Thomas, D.E., Lagnese, E.D., Walker, R.A., Nestor, J.A., Rajan, J.V., Blackburn, R.L. (1990). Control Step Scheduling (CSTEP). In: Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench. The Kluwer International Series in Engineering and Computer Science, vol 85. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1519-3_5
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DOI: https://doi.org/10.1007/978-1-4613-1519-3_5
Publisher Name: Springer, Boston, MA
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