Multiple-Valued Logic Minimization

Abstract

As discussed in Chapter 1, many multiple-valued input logic functions can be implemented very efficiently in PLA’s with two-bit input decoders. Hence multiple-valued logic minimization is of great practical importance [FLE 75]. A two-bit decoder pairs two Boolean variables, say x₁ and x₂, and generates four decodes

$$ \begin{array}{*{20}{c}} {{{x}_{1}}{{x}_{2}},} \\ {{{{\bar{x}}}_{1}}{{x}_{2}},} \\ {{{x}_{1}}{{{\bar{x}}}_{2}},} \\ {{{{\bar{x}}}_{1}}{{{\bar{x}}}_{2}}.} \\ \end{array} $$