Abstract
As you verify your design, you need to write a great deal of code, most of which is in tasks and functions. SystemVerilog introduces many incremental improvements to make this easier by making the language look more like C, especially around argument passing. If you have a background in software engineering, these additions should be very familiar.
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© 2012 Springer Science+Business Media, LLC
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Spear, C., Tumbush, G. (2012). Procedural Statements and Routines. In: SystemVerilog for Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0715-7_3
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DOI: https://doi.org/10.1007/978-1-4614-0715-7_3
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