Skip to main content

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 166))

Abstract

In a complete physical synthesis flow, many optimizations are applied to critical paths that are already optimized by a series of powerful transformations, as described in Chap. 2. Transforms that can further improve the timing of such paths are invaluable for timing closure. Finding such transformations and applying them efficiently is challenging.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Without loss of generality, we assume \(n\) and \(m\) are of the same order for simplicity of the complexity analysis.

References

  1. Ku?nar R, Brglez F (1995) PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. In: ICCAD, pp 644–649

    Google Scholar 

  2. Hwang J, El Gamal A (1992) Optimal replication for min-cut partitioning. In: ICCAD, pp 432–435

    Google Scholar 

  3. Chen G, Cong J (2005) Simultaneous timing-driven placement and duplication. In: ISFPGA, pp 51–59

    Google Scholar 

  4. Kim H, Lillis J, Hrkic M (2006) Techniques for improved placement-coupled logic replication. In: GLSVLSI, pp 211–216

    Google Scholar 

  5. Chen C, Tsui C (1999) Timing optimization of logic network using gate duplication. In: ASP-DAC, pp 233–236

    Google Scholar 

  6. Lillis J, Cheng CK, Lin TY (1996) Algorithms for optimal introduction of redundant logic for timing and area optimization. In: ISCAS, pp 452–455

    Google Scholar 

  7. Srivastava A et al (2001) On the complexity of gate duplication. IEEE Trans CAD 20(9):1170–1176

    Google Scholar 

  8. Srivastava A et al (2004) Timing driven gate duplication. IEEE Trans VLSI 12(1):42–51

    Article  Google Scholar 

  9. Saxena P, Menezes N, Cocchini P, Kirkpatrick DA (2004) Repeater scaling and its impact on CAD. IEEE Trans CAD 23(4):451–463

    Google Scholar 

  10. Bañeres D, Cortadella J, Kishinevsky M (2007) Layout-aware gate duplication and buffer insertion. In: DATE, pp 1367–1372

    Google Scholar 

  11. Alpert CJ et al (2006) Accurate estimation of global buffer delay within a floorplan. IEEE Trans TCAD 25(6):1140–1146

    Google Scholar 

  12. Otten R (1998) Global wires harmful. In: ISPD, pp 104–109

    Google Scholar 

  13. Luo T, Papa DA, Li Z, Sze CN, Alpert CJ, Pan DZ (2008) Pyramids: an efficient computational geometry-based approach for timing-driven placement. In: ICCAD, pp 204–211

    Google Scholar 

  14. Shi W, Li Z, Alpert CJ (2004) Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. In: ASP-DAC, pp 609–614

    Google Scholar 

  15. Chao TH et al (1992) Zero skew clock routing with minimum wirelength. IEEE Trans CAS 39(11):799–814

    MATH  Google Scholar 

  16. Li Z, Sze CN, Alpert CJ, Hu J, Shi W (2005) Making fast buffer insertion even faster via approximation techniques. In: ASP-DAC, pp 13–18

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media New York

About this chapter

Cite this chapter

Papa, D.A., Markov, I.L. (2013). Physically-Driven Logic Restructuring. In: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits. Lecture Notes in Electrical Engineering, vol 166. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1356-1_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-1356-1_6

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-1355-4

  • Online ISBN: 978-1-4614-1356-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics