Abstract
Cache miss rate reduction represents the classical approach to improving cache performance. On method to reduce cache miss rate is higher associativity cache. In this paper we introduce a novel method to enhance cache performance by dynamically choosing the best associativity that can be used to reduce cache miss rate depending on the running program needs. According to our approach cache can be move from direct mapped to 8-way associative online without the need to perform complex address mapping.
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References
Hennessy JL, Patterson DA (2003) Computer architecture: a quantitative approach. Morgan Kaufmann Publishers, San Fransisco
Kharbutli M, Irwin K, Solihin Y, Lee J (2011) Using prime numbers for cache indexing to eliminate conflict misses. This work was supported in part by North Carolina State University, Seoul National University, the Korean Ministry of Education under the BK21 program, and the Korean Ministry of Science and Technology under the National Research Laboratory program
Kharbutli M, Solihin Y (2008) Counter-based cache replacement and bypassing algorithms, IEEE Trans Comput 57(4):433–447
Ghasemzadeh H, Mazrouee S, Moghaddam HG, Shojaei H, Kakoee MR (2006) Hardware implementation of stack-based replacement algorithms. In: Proceedings of world academy of science, engineering and technology, vol 16
Beyls K, D’Hollander EH (2008) Refactoring intermediately executed code to reduce cache capacity misses. J Instr Lev Parallelism 10:1–9 (Submitted 10/06; published 6/08). This article initially appeared in abbreviated form in ACM computing frontiers 2006
Solihin Y, Lee J, Torrellas J (2003) Correlation prefetching with a user-level memory thread. In: IEEE Trans Parallel Distributed Syst 14(6):563–580
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AbuZaher, M., Alayoubi, B., Alefeshat, B., Mesleh, A. (2013). Dynamic Cache Miss-Rate Reduction. In: Elleithy, K., Sobh, T. (eds) Innovations and Advances in Computer, Information, Systems Sciences, and Engineering. Lecture Notes in Electrical Engineering, vol 152. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3535-8_16
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DOI: https://doi.org/10.1007/978-1-4614-3535-8_16
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