Abstract
This chapter describes the techniques and practices for achieving a low power implementation of the design. These implementation techniques provide power savings over and above those achieved by using the appropriate low power architecture. There are various techniques available and this chapter provides a sampling and an overview of the existing approaches.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Standard Vt is sometimes referred to as Regular Vt.
- 2.
See [BHA10].
- 3.
Built with minimum clock skew.
- 4.
On-Chip Variation.
- 5.
The substrate connections can be built in the standard cells or can be through separate “tub-tie” cells.
- 6.
- 7.
Voltage drop in power mesh rails.
- 8.
Also sometimes referred to as in-rush current.
- 9.
Unlike the memory array power supply which must be kept above a specified minimum to ensure no loss of contents, the peripheral logic power supply can be reduced to a much lower value.
- 10.
The memory core array power supply is removed in shutdown mode where the memory contents do not need to be saved.
References
[BHA10] Bhasker J., A SystemVerilog Primer, Star Galaxy Publishing, 2010, ISBN 978-0-9650391-1-6.
[STR05] Streetman B. and S. Bannerjee, Solid-state Electronic Devices, 6th edition, Prentice Hall, 2005.
[SZE81] Sze S.M., Physics of Semiconductor Devices, Second Edition, John Wiley & Sons, 1981.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Chadha, R., Bhasker, J. (2013). Low Power Implementation Techniques. In: An ASIC Low Power Primer. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4271-4_7
Download citation
DOI: https://doi.org/10.1007/978-1-4614-4271-4_7
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-4270-7
Online ISBN: 978-1-4614-4271-4
eBook Packages: EngineeringEngineering (R0)