Abstract
Capacitive DC–DC converters are switched-mode power supplies and thus inevitably generate switching noise. But a fully integrated DC–DC converter is also part of a SoC. Therefore the noise influences the other building blocks of the SoC. It is shown in this chapter that noise mitigation in fully integrated DC–DC converters has a certain cost, related to the chip area that is required to achieve this. The resilience of the other building blocks with respect to the noise generated by the DC–DC converter determines the acceptable level of noise and as a consequence the converter’s cost.
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Notes
- 1.
The voltage across the bond-wire is proportional with the time derivative of the current through the bond-wire: \(V_{L}=\frac{LdI}{dt}\).
- 2.
In this case only the charge leakage through the oxide is modeled. It is generally accepted that this leakage component is the dominant leakage phenomenon in CMOS integrated capacitors. (Rius and Meijer 2004).
- 3.
A digital load can be modeled as a capacitor switching between the supply and the ground and thus his behavior resembles a (switched-capacitor) resistor.
- 4.
By using separate ground connections and isolating the substrate by means of well’s, pockets or guard rings.
- 5.
The peak current is reduced with a factor \(N_{MP}\) since the switch resistance increased by a factor \(N_{MP}\).
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Van Breussegem, T., Steyaert, M. (2013). Noise Reduction by Multi-Phase Interleaving and Fragmentation. In: CMOS Integrated Capacitive DC-DC Converters. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4280-6_4
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DOI: https://doi.org/10.1007/978-1-4614-4280-6_4
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