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Coarse-Grained Reconfigurable Array Architectures

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Handbook of Signal Processing Systems

Abstract

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. Unlike VLIWs, CGRAs are designed to execute only the loops, which they can hence do more efficiently. This chapter discusses the basic principles of CGRAs and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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Authors and Affiliations

  1. Ghent University, Sint-Pietersnieuwstraat 41, 9000, Gent, Belgium

    Bjorn De Sutter

  2. IMEC, Kapeldreef 75, 3001, Heverlee, Belgium

    Praveen Raghavan & Andy Lambrechts

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  1. Bjorn De Sutter
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  2. Praveen Raghavan
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  3. Andy Lambrechts
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Correspondence to Bjorn De Sutter .

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  1. , Dept. of Electrical and, University of Maryland, A. V. Williams Bldg. 2311, College Park, 20742, Maryland, USA

    Shuvra S. Bhattacharyya

  2. Leiden Inst. Advanced Computer Science, Leiden Embedded Research Center, Leiden University, Niels Bohrweg 1, Leiden, 2333 CA, Netherlands

    Ed F. Deprettere

  3. Software for Systems on Silicon, RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

    Rainer Leupers

  4. , Department of Pervasive Computing, Tampere University of Technology, Korkeakoulunkatu 1, Tampere, 33720, Finland

    Jarmo Takala

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De Sutter, B., Raghavan, P., Lambrechts, A. (2013). Coarse-Grained Reconfigurable Array Architectures. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_18

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