Abstract
Decomposition with the parametric representation has been a direct enabler for several large verifications accomplished using symbolic simulation. In this chapter, two verification examples from Intel processor designs are presented. In contrast with the verifications reported in Chapter 3, these verifications involved hand-crafted formal specifications. The tests were performed on the same verification platform described in Section 3.1.1. Both verifications reasoned about the correctness of the circuit datapaths and did not consider the correctness of the pipelines.
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© 2002 Springer Science+Business Media New York
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Jones, R.B. (2002). Using the Parametric Representation. In: Symbolic Simulation Methods for Industrial Formal Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1101-4_5
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DOI: https://doi.org/10.1007/978-1-4615-1101-4_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5395-9
Online ISBN: 978-1-4615-1101-4
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