Skip to main content
SpringerLink
Log in

Underfill: The Enabling Technology for Flip-Chip Packaging

  • Chapter
Area Array Interconnection Handbook

Abstract

Organic polymer reinforcement of area-array solder connections between semiconductor chips and substrates has become an essential part of flip-chip packaging. Although flip-chip interconnection, or controlled collapse chip connection (C4) as it is also known, has a long history prior to the use of any reinforcement [1]; the use of a polymeric material to surround the solder connections beneath attached chips has allowed flip chips with large die footprints and increased neutral point distances to be utilized even with organic chip carriers.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. N. G. Koopman, T. C. Reiley and P. A. Totta,“Chip-to-package Interconnections,” Microelectronics Packaging Handbook, R.R. Tummala and E. J. Rymaszewski, eds., New York: Van Nostrand Reinhold, 1989, pp. 361–453.

    Google Scholar 

  2. K. J. Puttlitz and H. Quinones, “Flip Chip Solder Interconnections: A Reliability Perspective,” Proc. TMS Ann. Meeting (Orlando, FL), pp. 359–366, Feb. 1997.

    Google Scholar 

  3. K. Beckham, A. Kolman and K. Puttlitz, “Solder Interconnection Structure for Joining Semiconductor Devices to Substrates that have Improved Fatigue Life and Process for Making,” U.S. Patent 4, 604,644 (1986).

    Google Scholar 

  4. H. M. Tong, L. Mok, K. R. Grebe, H. L. Yeh, K. K. Srivastava and J. T. Coffin, “Parylene Encapsulation of Ceramic Packages for Liquid Nitrogen Applications,” Proc. 40th IEEE Electr. Comp. Technol Conf. (Las Vegas, NV), pp. 345–350, May 1990.

    Google Scholar 

  5. H. M. Tong, L. S. Mok, K. R. Grebe, H. L. Yeh, K. K. Srivastava and J. T. Coffin, “Effects of Parylene Coating on the Thermal Fatigue Life of Solder Joints in Ceramic Packages,” IEEE Trans. Comp., Hybr. Manuf.TechnoL, 16 (5): pp. 571–575, 1993.

    Google Scholar 

  6. F. Nakano, T. Soga and S. Amagi, “Resin Insertion Effect on Thermal Cycle Resistivity of Flip Chip Mounted LSI Devices,” Proc. Int. Symp. Microelectr. (Minneapolis, MN), pp. 536–541, Sept. 1987.

    Google Scholar 

  7. J. G. Ameen, G. O. Dearing, S. L. Buchwalter, C. A. Kovac, J. Poler and P. A. Poore, IBM, Unpublished results, 1987.

    Google Scholar 

  8. J. Coffin, IBM, Unpublished results, 1987.

    Google Scholar 

  9. K. I. Papathomas, F. R. Christie and D. W. Wang, IBM, Unpublished results, 1991.

    Google Scholar 

  10. D. W. Wang and K. I. Papathomas, “En-capsulant for Fatigue Life Enhancement of Controlled Collapse Chip Connection (C4),” IEEE Trans. CHMT, 16(8): pp. 863–867, 1993.

    Google Scholar 

  11. D. Suryanarayana, R. Hsiao, T. P. Gall and J. M. McCreary, “Enhancement of Flip Chip Fatigue Life by Encapsulation,” IEEE Trans. CHMT,14(1): pp. 218–223,1991.

    Google Scholar 

  12. Y. Tsukada, Y. Mashimoto, T. Nishio and N. Mii, “Reliability and Stress Analysis of Encapsulated Flip Chip Joint on Epoxy Base Printed Circuit Board,” Proc. Joint ASME/JSME Conf. Electr. Packag. (Milpitas, CA), pp. 827–835, Apr. 1992.

    Google Scholar 

  13. T. Soga, M. Goda, F. Nakano, N. Ushifusa, F. Kobayashi and M. Sawahata, “Solder Resin Package Structure,” U.S. Patent 4,825,284 (1989).

    Google Scholar 

  14. Y. Tsukada, “Solder Bumped Flip Chip Attach on SLC Board and Multichip Module,” Chip on Board Technologies for Multichip Modules, J. H. Lau, ed., New York, NY: Van Nostrand Reinhold,1994, pp. 410–443.

    Google Scholar 

  15. A. J. Babiarz, “Key Process Controls for Underfilling Flip Chips,” Solid State Technol, 40(4): pp. 77–83,1997.

    Google Scholar 

  16. R. L. Jackson, P. Carnevali and J. D. Frazier, “Finite Element Modeling of Encapsulated Fip Chip Packaging Assemblies,” Proc. Int. Symp. Microelectr. (Orlando, FL), pp. 82–85, Oct. 1991.

    Google Scholar 

  17. J. H. Lau, “Thermal Fatigue Life Prediction of Encapsulated Flip Chip Solder Joints for Surface Laminar Packaging,” Proc. ASME Winter Ann. Meeting (Anaheim, CA), pp. 1–9, Nov.1992.

    Google Scholar 

  18. C. Z. Yeh, X. Wen, A. Skipor and K. Wyatt, “Parametric Finite Element Analysis of Flip Chip on Board Reliability,” Int. J. Microcirc. Elect. Packag., 19 (2): pp. 120–127, 1996.

    Google Scholar 

  19. X. Dai, C. Kim, R. Willecke and P. S. Ho, “In-situ Mapping and Modeling Verification of Thermomechanical Deformation in Under-filled Flip-chip Packaging using Moire Interferometry,” MRS Symp. Proc., 445: pp. 167–177,1997.

    Google Scholar 

  20. S. F. Popelar, “Parametric Study of Flip Chip Reliability Based on Solder Fatigue Modelling,” Proc. IEEE/CPMT Int. Electr. Manuf. Technol. Symp. (Austin, TX), pp. 299–307, Oct. 1997.

    Google Scholar 

  21. J. Clementi, J. McCreary, T. M. Niu, J. Palomaki, J. Varcoe and G. Hill, “Flip Chip Encapsulation of Ceramic Substrates,” Proc. 43rd IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 175–181, June 1993.

    Google Scholar 

  22. D. O. Powell and A. K. Trivedi, “Flip Chip on FR4 Integrated Circuit Packaging,” Proc. 43rd IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 182–186, June 1993.

    Google Scholar 

  23. D. Gamota and C. M. Melton, “Advanced Encapsulant Materials Systems for Flip Chip on Board Assemblies. I. Encapsulant Materials with Improved Manufacturing Properties. II. Materials to Integrate the Re-flow and Underfilling Processes,” Proc. 19th IEEE/CPMT Int. Electr. Manuf. Technol. Symp. (Austin, TX), pp. IBM. 1–9, Oct. 1996.

    Google Scholar 

  24. C. Beddingfield and L. Higgins, “Moisture Sensitivity and Component Reliability of Flip Chip PBGA Assemblies,” Proc. Int. Electr. Packag. Soc. Conf. (Austin, TX), pp. 26–36, Sept. 1996.

    Google Scholar 

  25. A. F. J. Baggerman, J. E. J. M. Caers, J. J. Wondergem and A. G. Wagemans, “Low Cost Flip Chip on Board,” IEEE Trans. CPMT-B, 19(4): pp. 736–746,1996.

    Google Scholar 

  26. S. Han, K. K. Wang and S. Y. Cho, “Experimental and Analytical Study on the Flow of Encapsulant during Underfill Encapsulation of Flip-chips,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 327–334, May 1996.

    Google Scholar 

  27. J. Lau, C. Chang and R. Chen, “Effects of Underfill Encapsulant on the Mechanical and Electrical Performance of a Functional Flip Chip Device,” Proc.1st IEEE Int. Symp. Polym. Electr. Packag. (Norrkoping, Sweden), pp. 265–272, Oct. 1997.

    Google Scholar 

  28. D. F. Baldwin and N. W. Pascarella, “Manufacturability of Underfill Processing for Low Cost Flip Chip,” Proc. ASME Int. Mech. Eng. Congr. (Dallas, TX), pp. 21–31, Nov. 1997.

    Google Scholar 

  29. D. Zoba and M. E. Edwards, “Review of Underfill Encapsulant Development and Performance of Flip Chip Applications,” Int. Symp. Microelectr. (Los Angeles, CA), pp. 354–358, Oct. 1995.

    Google Scholar 

  30. W. Koh, “Encapsulants for Chip on Board and Chip Scale Packaging,” Proc. 1st Pan Pacific Microelectr. Symp. (Honolulu, HI), pp. 133–136, Feb. 1996.

    Google Scholar 

  31. D. M. Shi and J. W. Carbin, “Advances in Flip-chip Underfill Flow and Cure Rates and Their Enhancement of Manufacturing Processes and Component Reliability,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 1025–1031, May 1996.

    Google Scholar 

  32. “The New HEL Series Underfills Offer Fast Flow, Snap Cure and Instrinsic Strain Relief”Alpha Metals, Inc.; Electronic Polymers Group, 1998, http://ww.alphapolymers.com/hel.html

  33. Y. Tsukada, Y. Mashimoto and N. Watanuki, “Novel Chip Replacement Method of Encapsulated Flip Chip Bonding,” Proc. 43rd IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 199–204, June 1993.

    Google Scholar 

  34. E L. Pompeo, A. J. Call, J. T. Coffin and S. L. Buchwalter, “Reworkable Encapsulation for Flip Chip Packaging,” EEP Adv. Electr. Packag. 10(2): pp. 781–787,1995.

    Google Scholar 

  35. JEDEC, “Moisture-Induced Stress Sensitivity for Plastic Surface Mount Devices: EIA/JEDEC Standard EIA/JESD22–A112A,” Electronic Industries Association Report, Nov. 1995.

    Google Scholar 

  36. D. R. Gamota, Motorola Corp., Unpublished results, 1997.

    Google Scholar 

  37. G. W. De Vos, Nat. Electr. Manuf. Init. Interconn. Technol. Res. Inst., Unpublished results, 1998.

    Google Scholar 

  38. J. M. Rosson, R. A. Clawson and D. W. Ihms, “Underfill Test Methods for the Harsh Automotive Environment,” Adv. Packag., 8(1): pp. 48–53,1999.

    Google Scholar 

  39. M. R. Witty et al., “Flip Chip Assembly on Rigid Organic Laminates: A Production-ready Process for Automotive Electronics,” Int. Conf. MCM & High Dens. Packag. (Denver, CO), pp. 64–69, Apr. 1998.

    Google Scholar 

  40. G. Kromann, “Thermal Management of a C4/CBGA Interconnect Technology for a High Performance RISC Microprocessor: The Motorola PowerPC 620TM Microprocessor,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL Motorola Corp), pp. 652–659, May 1996.

    Google Scholar 

  41. R. Master, T. Dolbear, M. Cole and G. Martin, “Ceramic Ball Grid Array for AMD K6 Microprocessor Application,” Proc. 48th IEEE Electr. Comp. & Technol. Conf. (Seattle, WA), pp. 702–706, May 1998.

    Google Scholar 

  42. “Intel Pentium II Mini-Cartridge,” Prismark Partners LLC Report, June 1998.

    Google Scholar 

  43. H. Matsushma, S. Baba, Y. Tomita, M. Watanae, E. Hayashi and Y. Takemoto, “Thermally Enhanced Flip-chip BGA with Organic Substrate,” Proc. 48th IEEE Electr. Comp. & Technol. Conf. (Seattle, WA), pp. 685–691, May 1998.

    Google Scholar 

  44. T. Patterson, “A Practical Versatile Approach to Flip Chip on Flex,” Proc. Surface Mount Int. Conf. (San Jose, CA), pp. 110–114, Aug. 1995.

    Google Scholar 

  45. H. Lowe and R. Lyn, “Real World Flip Chip Assembly: a Manufacturer’s Experiences,” Proc. Surface Mount Int. Conf. (San Jose, CA), pp. 80–87, Aug. 1995.

    Google Scholar 

  46. R. Doot, “Motorola’s First DCA Product: The Gold Line Pen Pager,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 535–539, May 1996.

    Google Scholar 

  47. M. E. Edwards, Dexter Electronic Materials, Unpublished results, 1995.

    Google Scholar 

  48. D. Zoba, Dexter Electronic Materials, Unpublished results, 1997.

    Google Scholar 

  49. D. R. Gamota and C. M. Melton, “Advanced Encapsulant Systems for Flip-chip-on-board Assemblies: Underfills with Improved Manufacturing Properties,” IEEE Trans. CMPT-C, 21(3): pp.196–203,1998.

    Google Scholar 

  50. C. Naito, Dexter Electronic Materials, Unpublished results, 1996.

    Google Scholar 

  51. V. Gektin, A. Bar-Cohen and J. Ames, “Coffin-Manson Fatigue Model of Under-filled Flip-chips,” IEEE Trans. CPMT-A, 20(3): pp. 317–326,1997.

    Google Scholar 

  52. H. H. Manko, Solders and Soldering, New York: McGraw-Hill, Inc., 1992, 3rd edition, pp. 117.

    Google Scholar 

  53. M. E. Edwards, Dexter Electronic Materials, Unpublished results, 1996.

    Google Scholar 

  54. T. Y. Wu and G. H. Thiel, “Fracture Toughness of Flip Chip Encapsulants,” Appi. Fract. Mech. Electr. Packag. Matis. (San Francisco, CA), pp. 205–210, Nov. 1995.

    Google Scholar 

  55. H. W. Rauhut, “Low-Alpha Epoxy Molding Compounds,” SPE Ann. Tech. Conf, 49: pp. 1260–1264,1991.

    Google Scholar 

  56. M. E. Edwards, “Factors Affecting Flip Chip Underfill Performance,” Proc. 4th Int. Symp. Adv. Packag. Matis. Proc. Prop. Interfaces (Braselton, GA), pp. 21–28, Mar. 1998.

    Google Scholar 

  57. C. Beddingfield and L. Higgins, III, “Effects of Flux Materials on the Moisture Sensitivity and Reliability of Flip Chip on Board Assemblies,” Proc. IEEE/CPMT Int. Electr. Manuf. Technol. Symp. (Austin, TX), pp. 6–11, Oct. 1997.

    Google Scholar 

  58. S. L. Buchwalter, M. Gaynes, S. Tran and N. LaBianca, IBM Corporation, Unpublished results, 1999.

    Google Scholar 

  59. M. A. Gaynes and S. Tran, Unpublished results, IBM Corporation, 1996.

    Google Scholar 

  60. E. P. Plueddemann, Silane Coupling Agents, New York: Plenum Press, 1982.

    Google Scholar 

  61. M. B. Vincent, L. Meyers and C. P. Wong, “Enhancement of Underfill Performance for Flip-chip Applications by Use of Silane Additives,” Proc. 48th IEEE Electr. Comp. & Technol. Conf. (Seattle, WA), pp. 125–131, May 1998.

    Google Scholar 

  62. S. Tran, D. L. Questad and B. G. Sammakia, “Adhesion Issues in Flip Chip on Organic Modules,” ITherm’98. 6th Intersoc. Conf. on Thermal and Thermomech. Phenom. in Electr. Syst. (Seattle, WA), pp. 263–268, May 1998.

    Google Scholar 

  63. H. Doi, K. Kawano, A. Yasukawa and T. Sato, “Reliability of Underfill-Encapsulated Flip-chip Packages,” Proc. ASME Int Mech. Eng. Congr. (Dallas, TX), pp. 7–14, Nov. 1997.

    Google Scholar 

  64. D. R. Gamota and C. M. Melton, “En-capsulant Materials Systems for Flip Chip on Board Assemblies: Addressing Manufacturing Issues,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 24–32, Feb. 1997.

    Google Scholar 

  65. E. Cotts, personal communication.

    Google Scholar 

  66. D. Suhrbur and D. R. Gamota, “Evaluation of High Performance Encapsulants for FCOB: Phase 1,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 1094–1100, Mar. 1998.

    Google Scholar 

  67. W. H. Leong, “Developing an Underfill Process for Dense Flip Chip Applications,” Proc. 19th IEEE/CPMT Int. Electr. Manuf. Technol. Symp. (Austin, TX), pp. 10–17, Oct. 1996.

    Google Scholar 

  68. S. Michaelides and S. Sitaraman, “Role of Underfilling Imperfections on Flip Chip Reliability,” EEP Adv. Electr. Packag., 19–2: pp. 1487–1493,1997.

    Google Scholar 

  69. E. J. Cotts, T. Driscoll, N. R. Guydosh, G. Lehmann and P. Li, “Underflow Process for Direct-chip-attachment Packaging,” Proc. 1st IEEE Int Symp. Polym. Electr. Packag. (Norrkoping, Sweden), pp. 273–283, Oct. 1997.

    Google Scholar 

  70. A. J. Babiarz, “Die Encapsulation and Flip Chip Underfilling Processes for Area Array Packaging of Advanced Integrated Circuits,” Proc. 2nd Pan Pacific Microelectr. Symp. (Maui, HI), pp. 123–125, Jan. 1997.

    Google Scholar 

  71. A. Lewis and A. J. Babiarz, “Automatic Dispensing Process for Underfilling Flip Chip on Board,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 316–326, Feb. 1997.

    Google Scholar 

  72. G. Lehmann, A. Maria, P. C. Lee and E. J. Cotts, “Modeling the Underfill Flow Process-Direct Chip Attach,” Proc. Surf Mount Int Adv. Electr. Manuf. (San Jose, CA), pp. 340–350, Sept. 1996.

    Google Scholar 

  73. T. E. Driscoll, P. C. Li, G. L. Lehmann and E. J. Cotts, “Investigation of the Flow Behavior of Particulate Filled Fluids,” MRS Symp. Proc., 445: pp. 69–74,1997.

    Google Scholar 

  74. G. L. Lehmann, T. Driscoll, N. R. Guydosh, P. C. Li and E. J. Cotts, “Underflow Process for Direct Chip Attachment Packaging,” IEEE Trans. CPMT-A, 21(2): pp. 266–274, 1998.

    Google Scholar 

  75. N. E. Iwamoto, M. Li, S. J. McCaffery, M. Nakagawa and G. Mustoe, “Molecular Dynamics and Discrete Element Modeling Studies of Underfill,” Int. J. Microcircuits Electr. Packag. (USA), 21(4): pp. 322–328, 1998.

    Google Scholar 

  76. N. E. Iwamoto, M. Nakagawa and G. Mustoe, “Predicting Material Trends Using Discrete Newtonian Modeling Techniques,” NEP-CON Proc. Tech. Prog. (Anaheim, CA), pp. 1689–1698, Feb. 1999.

    Google Scholar 

  77. J. A. Emerson and C. L. J. Adkins, Sandia National Laboratory, Unpublished results, 1999.

    Google Scholar 

  78. D. Suryanarayana and D. Farquhar, “Underfill Encapsulation for Flip Chip Application,” Chip on Board: Technologies for Multichip Modules, J. Lau, ed., New York: Van Nostrand Reinhold, 1994, pp. 504–531.

    Google Scholar 

  79. R. J. Lyn, “Encapsulation for PCMCIA Assemblies,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 743–751, Feb. 1993.

    Google Scholar 

  80. O. Diaz De Leon, M. Nassirian, C. Todd and R. Chowdhury, “Failure Analysis of Flip Chip Interconnections Through Acoustic Microscopy,” Proc. 22nd Int. Symp. Test. Failure (Los Angeles, CA), pp. 227–283, Nov. 1996.

    Google Scholar 

  81. C. P. Yeh, W. X. Zhou, A. Skipor and K. Wyatt, “Parametric Finite Element Analysis of Flip Chip on Board Reliability,” Proc. Int. Electr. Packag. Soc. Conf. (San Diego, CA), pp. 297–306, Sept. 1995.

    Google Scholar 

  82. S. Ha, “Underfill Process Development for SLICC,” Proc. 2nd Pan Pacific Microelectr. Symp. (Maui, HI), pp. 417–420, Jan.1997.

    Google Scholar 

  83. M. Bonneau and J. Stewart, “Reduced Cycle Time Epoxies for Flip Chip Underfill,” Proc. 3rd Int. Symp. Adv. Packag. Marls. Proc. Prop. Interfaces (Braselton, GA), pp. 57–61, Mar. 1997.

    Google Scholar 

  84. R. B. Prime, “Thermosets,” Thermal Characterization of Polymeric Materials, E. Turi, ed., New York: Academic Press, 1997, 2nd edition, pp. 1555–1559.

    Google Scholar 

  85. S. Yegnasubramanian et al., “Flip-chip-onboard (FCOB) Assembly and Reliability,” Proc. 21st IEEE/CPMT Int. Electr. Manuf. Technol. Symp. (Austin, TX), pp. 32–36, Oct. 1997.

    Google Scholar 

  86. J. B. Nysaether, P. Lundstrom and J. Liu, “Measurements of Solder Bump Lifetime as a Function of Underfill Material Properties,” Proc. 1st IEEE Int. Symp. Polym. Electr. Packag. (Norrkoping, Sweden), pp. 307–314, Oct. 1997.

    Google Scholar 

  87. V. Gektin, A. Bar-Cohen and S. Witz-man, “Thermo-structural Behavior of Underfilled Flip-chips,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL, USA), pp. 440–447, May 1996.

    Google Scholar 

  88. A. Schubert, R. Dudek, B. Michel, H. Reichl and H. Jiang, “Materials Mechanics and Mechanical Reliability of Flip Chip Assemblies on Organic Substrates,” Proc. 3rd Int. Symp. Adv. Packag. Matis. Proc. Prop. Interfaces (Braselton, GA), pp. 106–109, Mar. 1997.

    Google Scholar 

  89. C. P. Wong, R. Tummala, J. Qu and S. Sitaraman, “Microelectronic Package Trends-the Role of Reliability in Particularly, Related to Solder Joints Reliability,” Proc. TMS Ann. Meeting (Orlando, FL), pp. 3–8, Feb. 1997.

    Google Scholar 

  90. M. A. Gaynes, R. E Saraf and J. M. Roldan, “Evaluation of Contact Resistance for Isotropically Electrically Conductive Adhesives,” IEEE Trans. CPMT-B, 18(2): pp. 299–304,1995.

    Google Scholar 

  91. L. White and D. Suryanarayana, “Flip chip Encapsulation for MCM-L,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 1493–1502, Feb. 1994.

    Google Scholar 

  92. S. Tran, IBM Corporation, Unpublished results, 1994.

    Google Scholar 

  93. B. Miles and B. Freyman, “The Elimination of the Popcorn Phenomenon in Overmolded Plastic Pad Array Carriers (OMPAC),” Proc. Tech. Conf. IEPS (Austin, TX), pp. 605–614, Sept. 1992.

    Google Scholar 

  94. K. Darbha, J. H. Okura and A. Dasgupta, “Impact of Underfill Filler Particles on Reliability of Flip Chip Interconnects,” IEEE Trans. CPMT-A, 21(2): pp. 275–280, 1997.

    Google Scholar 

  95. J. Cincotta, IBM Corporation, Unpublished results, 1997.

    Google Scholar 

  96. H. Nied, Lehigh University, Unpublished results, 1999.

    Google Scholar 

  97. T. Y. Wu, Y. Tsukada and W. T. Chen, “Materials and Mechanics Issues in Flip-chip Organic Packaging,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 524–534, May 1996.

    Google Scholar 

  98. C. A. Le Gall, J. Qu and D. L. McDowell, “Delamination Cracking in Encapsulated Flip Chips,” Proc. 46th IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 430–434, May 1996.

    Google Scholar 

  99. D. Peterson, Sandia National Laboratories, Unpublished results, 1999.

    Google Scholar 

  100. S. Rzepka, M. A. Korhonen, E. Meusel and C. Y. Li, “Effect of Underfill Delamination on the Reliability of Chip Modules,” Proc. ASME Int. Mech. Eng. Congr.(Dallas, TX),pp. 73–83, Nov. 1997.

    Google Scholar 

  101. X. Dai, M. V. Brillhart and P. S. Ho, “Investigation of Underfill Adhesion in Plastic Flip-chip Packages,” Appi. of Fract. Mech. in Electr. Packag. ASME (Dallas, TX), pp. 115–124, s 1997.

    Google Scholar 

  102. C. E. Park, B. J. Hah and H. E. Bair, “Humidity Effects on Adhesion Strength between Solder Ball and Epoxy Underfills,” Polymer, 38(15): pp. 3811–3818,1997.

    Google Scholar 

  103. J. Jiao, Y. Sha, C. K. Gurumurthy, C. Y. Hui, E. J. Kramer and B. Peter, “Effect of Thermal Residual Stress on the Measurement of the Adhesion between Polyimide and Underfill using an Asymmetric Double Cantilever Beam Specimen,” Proc. ASME Int. Mech. Eng. Congr. (Dallas, TX), pp. 97–102, Nov. 1997.

    Google Scholar 

  104. Y. Sha, C. Y. Hui, E. J. Kramer, P. Borgesen, and G. Westby, “Delamination Trends of Underfill in DCA Assemblies,” MRS Symp. Proc., 445: pp. 3–8,1997.

    Google Scholar 

  105. W. C. Zheng, S. V. Harren and A. F. Skipor, “Thermomechanical Analysis of Flip Chip on Board Electronic Packaging Assembly,” Proc. ASME Int. Mech. Eng. Congr. (Chicago, IL), pp. 1–5, Nov. 1994.

    Google Scholar 

  106. B. Han, Y. Guo, T. Chung and D. Liu, “Reliability Assessment of Flip Chip Package with Encapsulation,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 600–602, Feb.1995.

    Google Scholar 

  107. J. H. Lau, “Solder Joint Reliability of Flip Chip and Plastic Ball Grid Array Assemblies under Thermal, Mechanical and Vibrational Conditions,” IEEE Trans. CPMT-B, 19(4): pp. 728–735.1996.

    Google Scholar 

  108. J. B. Nysaether, Z. Lai and Z. Liu, “Isotropically Conductive Adhesives and Solder Bumps for Flip Chip on Board Circuits: A Comparison of Lifetime under Thermal Cycling,” Proc. 3rd Int. Conf. Adh. Joining Coating Technol. Electr. Manuf. (Binghamton, NY), pp. 125–131, Sept. 1998.

    Google Scholar 

  109. G. O’Malley, J. Giesler and S. Machuga, “The Importance of Material Selection for Flip Chip on Board Assemblies,” Proc. 44th IEEE Electr. Comp. Technol. Conf. (Washington, DC), pp. 387–394, May 1994.

    Google Scholar 

  110. R. A. Pearson, T. B. Lloyd and R. Bagheri, “Adhesion Issues at Epoxy Underfill/Solder Mask Interfaces,” Proc. Surf. Mount Int. Adv. Electr. Manuf. Technol. (San Jose, CA), pp. 329–335, Sept. 1996.

    Google Scholar 

  111. C. K. Gurumurthy, J. Jiao, L. G. Norris, C.-Y. Hui and E. J. Kramer, “New Approach for Thermal Fatigue Testing of the Underfill/Passivation Interface,” Proc. ASME Int. Mech. Eng. Congr. (Dallas, TX), pp. 41–47, Nov. 1997.

    Google Scholar 

  112. M. A. Gaynes and H. Shaukatullah, “Evaluation of Thermally Conductive Adhesives for Bonding Heat Sinks to Electronic Packages,” Proc. 43rd IEEE Electr. Comp. Technol. Conf. (Orlando, FL), pp. 765–771, June 1993.

    Google Scholar 

  113. W. Hines and D. Montgomery, Probability and Statistics in Engineering and Management Science, New York: John Wiley & Sons, 1980, pp. 188–192.

    Google Scholar 

  114. A. Zubeliewicz, IBM Corporation, Unpublished results, 1998.

    Google Scholar 

  115. M. Gaynes, IBM Corporation, Unpublished results, 1999.

    Google Scholar 

  116. D. R. Gamota and C. M. Melton, “Development of Reflowable Materials Systems to Integrate the Reflow and Underfill Dispensing Processes for DCA/FCOB Assembly,” IEEE Trans. CMPT-C, 20(3): pp. 183–187, 1997.

    Google Scholar 

  117. M. Erickson and K. Kirsten, “Simplifying the Assembly Process with a Reflow/Encapsulant,” Electr. Packag. and Prod., 37(3): pp. 81–82,84,86,1997.

    Google Scholar 

  118. N. W. Pascarella and D. F. Baldwin, “Advanced Encapsulation Processing for Low Cost Electronics Assembly: A Cost Analysis,” Proc. 3rd Int. Symp. Adv. Packag. Matis. Proc. Prop. Interfaces (Braselton, GA), pp. 50–53, Mar. 1997.

    Google Scholar 

  119. C. P. Wong, D. Baldwin, M. B. Vincent, B. Fennell, L. J. Wang and S. H. Shi, “Characterization of a No Flow Underfill Encapsulant during the Solder Reflow Process,” Proc. 48th IEEE Electr. Comp. Technol. Conf. (Seattle, WA), pp. 1253–1259, May 1998.

    Google Scholar 

  120. C. P. Wong, S. H. Shi and G. Jefferson, “High Performance No Flow Underfills for Low Cost Flip Chip Applications: Material Characterization,” IEEE Trans. Compon. Packag. Manuf. Technol. A, 21(3): pp. 450–458,1998.

    Google Scholar 

  121. S. H. Shi and C. P. Wong, “Study of the Fluxing Agent Effects on the Properties of No-flow Underfill Materials for Flip-chip Applications,” Proc. 48th IEEE Electr. Comp. & Technol. Conf. (Seattle, WA), pp. 117–124, May 1998.

    Google Scholar 

  122. R. W. Johnson, M. A. Capote, S. Chu, L. Zhou and B. Gao, “Reflow Curable Polymer Fluxes for Flip Chip Encapsulation,” Proc. Int. Conf. MCM High Dens. Packag. (Denver, CO), pp. 41–46, Apr. 1998.

    Google Scholar 

  123. E. Jung, R. Aschenbrenner, E. Zakel and H. Reichl, “Flip Chip Interconnection to Organic Substrates: A Comparison between Adhesive Bonding and Soldering,” Proc. 10th Eur. Microlectr. Conf. (Copenhagen), pp. 44–53, May, 1995.

    Google Scholar 

  124. S. Hah and K. K. Wang, “Study on the Pressurized Underfill Encapsulation of Flip Chips,” IEEE Trans. CPMT-B, 20(4): pp. 431–442, 1997.

    Google Scholar 

  125. I. Ahmad, Z. Fathi, M. Konarski, D. Tucker and E. Yaeger, “A Look at Variable Frequency Microwave Curing,” Circuits Assem. (USA), 9(7): pp. 54, 56–58, 60–63,1998.

    Google Scholar 

  126. Z. Fathi et al., “Innovative Curing of High Reliability Advanced Polymeric Encapsulants,” NEPCON Proc. Tech. Prog. (Anaheim, CA), pp. 1084–1093, Mar. 1998.

    Google Scholar 

  127. B. Anderson et al., “Rapid Processing and Properties Evaluation of Flip Chip Under-fills,” NEPCONProc. Tech. Prog. (Anaheim, CA), pp. 1043–1051, Mar. 1998.

    Google Scholar 

  128. J. Qu and C. P. Wong, “Effective Elastic Modulus of Underfill Material for Flip-chip Applications,” Proc. 48th IEEE Electr. Comp. & Technol. Conf. (Seattle, WA), pp. 848–850, May 1998.

    Google Scholar 

  129. W. Chen, J. Gentile and L. Higgins, “FCOB Reliability Evaluation Simulating Multiple Rework/Reflow Processes,” IEEE Trans. CMPT-C, 19(4): pp. 270–276,1996.

    Google Scholar 

  130. W. Koh and D. Zoba, “A Study of Rework-able Flip Chip Encapsulants,” Int. J. Microcirc. Elect. Packag., 20(2): pp. 162–166, 1997.

    Google Scholar 

  131. D. Suryanarayana, J. A. Varcoe, and J. V. Ellerson, “Repairability of Underfill Encapsulated Flip-chip Packages,” Proc. 45th IEEE Electr. Comp. Technol. Conf. (Las Vegas, NV), pp. 524–528, May 1995.

    Google Scholar 

  132. M. Kelly and J. Lau, “Low Cost Solder Bumped Flipchip MCM-L Demonstration,” Circuit World, 21: pp. 14–17,1995.

    Google Scholar 

  133. S. L. Buchwalter and L. L. Kosbar, “Cleavable Epoxy Resins: Design for Disassembly of a Thermoset,” J. Polym. Sci. A: Chem.,34: pp. 249–260,1996.

    Google Scholar 

  134. S. Yang, J. Chen, H. Koerner, T. Bremner, C. K. Ober and M. Poliks, “Reworkable Epoxies: Thermosets with Thermally Cleavable Groups for Controlled Network Breakdown,” Chem. Matls. 10 (6): pp. 1475–1482, 1998.

    Google Scholar 

  135. L. Crane, A. Torres-Filho, C. K. Ober, S. Yang, J. S. Chen and R. W. Johnson, “Development of Reworkable Underfills, Materials, Reliability and Processing,” Proc. 3rd Int. Conf. Adh. Joining Coating Technol. Electr. Manuf. (Binghamton, NY), pp. 262–265, Sept. 1998.

    Google Scholar 

  136. J. B. Hall, P. B. Hogerton and J. M. Pujol, “Reversible Adhesive for Electronic Applications,” U.S. Patent 5,457,149 (1995).

    Google Scholar 

  137. A. J. Call et al., “Reworkable Polymer Chip Encapsulant,” U.S. Patent 5,659,203 (1997).

    Google Scholar 

  138. B. Ma, Q. Tong, A. Savoca, M. Bonneau and T. DeBarros, “Novel Fast Cure and Rework-able Underfills,” Proc. 4th Int. Symp. Adv. Packag. Matls. Proc. Prop. Interfaces (Braselton, GA), pp. 1–5, Mar. 1998.

    Google Scholar 

  139. S. R. Iyer and P. K. Wong, “Thermally Re-workable Binders for Flip Chip Devices,” U.S. Patent 5,760,337 (1998).

    Google Scholar 

  140. M. Schen, “Wafer-scale Applied Rework-able Fluxing Underfill for Direct Chip Attach,” NIST-ATP, 1998, http://jazz.nist.gov/atpcf/prjbriefs/prjbrief.cfm? ProjectNumber = 98–06–0008.

    Google Scholar 

  141. M. Schen, “Novel High-performance Wafer-level Reworkable Underfill Materials for Flip-chip Packaging,” NIST-ATP, 1998, http://jazz.nist.gov/atpcf/prjbriefs/prjbrief.cfm? ProjectNumber = 98–06–0030.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. IBM Research Division, USA

    Stephen L. Buchwalter

  2. Dexter Electronic Materials, USA

    Maurice E. Edwards

  3. Motorola Advanced Technology Center, USA

    Daniel Gamota

  4. IBM Microelectronics, USA

    Michael A. Gaynes & Son K. Tran

Authors
  1. Stephen L. Buchwalter
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Maurice E. Edwards
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Daniel Gamota
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Michael A. Gaynes
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Son K. Tran
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Karl J. Puttlitz Paul A. Totta

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer Science+Business Media New York

About this chapter

Cite this chapter

Buchwalter, S.L., Edwards, M.E., Gamota, D., Gaynes, M.A., Tran, S.K. (2001). Underfill: The Enabling Technology for Flip-Chip Packaging. In: Puttlitz, K.J., Totta, P.A. (eds) Area Array Interconnection Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1389-6_12

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-1389-6_12

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5529-8

  • Online ISBN: 978-1-4615-1389-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation