Abstract
The main problem in using the analysis strategy of the previous chapter is the exponential explosion of the space requirement for storing each of the responses and response constraints at each circuit element. This in turn causes an exponential explosion in run-time necessary to generate the responses. The approach described in this chapter relies on the fact that many of the event times of responses at a given circuit element will be identical (depending on the level of quantization of delay times). These responses with identical event times are collapsed into one response and the response constraints are stored implicitly in a Response Dependency Graph (RDG). In this way, the space requirement is drastically reduced, and the major time complexity becomes searching the RDG to determine if responses are actually possible.
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© 1994 Springer Science+Business Media New York
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Gray, C.T., Liu, W., Cavin, R.K. (1994). Exact Timing Analysis: Algorithm. In: Wave Pipelining: Theory and CMOS Implementation. The Kluwer International Series in Engineering and Computer Science, vol 248. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3206-4_5
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DOI: https://doi.org/10.1007/978-1-4615-3206-4_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6407-8
Online ISBN: 978-1-4615-3206-4
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