Abstract
We describe the modelling and simulation of a pseudosystolic processor for matrix algorithms. The processor follows the decoupled access/execute model of computation, and is therefore composed of two programmable units: an Access Unit (AU) and a Processing Unit (PU). Both units work independently and synchronize their operation through queues.
The modelling and simulation are based on a formal specification of the processor written in Verilog HDL, a high level language for hardware description. Such a specification describes the processor at the behavioral level (instruction set architecture) and at the structural level (register transfer architecture). Performance measures can be obtained through the simulation, making it possible to evaluate tradeoffs in the instruction set design as well as in lower levels of the architecture.
Hardware modelling and simulation are helping us to find bottlenecks in the architecture. Moreover, they are allowing us to evaluate the effectiveness of several features and their impact on overall system performance, thus proving to be an important tool in the development of complex digital systems.
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© 1992 Springer Science+Business Media New York
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Figueroa, M.E., Moreno, J.H. (1992). Modelling and Simulation of a Pseudosystolic Processor for Matrix Algorithms. In: Baeza-Yates, R., Manber, U. (eds) Computer Science. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3422-8_35
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DOI: https://doi.org/10.1007/978-1-4615-3422-8_35
Publisher Name: Springer, Boston, MA
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