Abstract
A number of researches have addressed the problem of minimizing power dissipation during module allocation and binding [RJ94] [KC97], scheduling and allocation [MC95], register allocation and binding [RJ94] [CP95a] and trading area for lower power through pipelining or parallelization combined with voltage scaling [GOC94] [CPRR92], scheduling using multiple supply voltages [CP96a, CP97] [RS95] [JR96].
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© 1999 Springer Science+Business Media New York
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Chang, JM., Pedram, M. (1999). Power-Optimal Module Allocation and Binding. In: Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5199-7_3
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DOI: https://doi.org/10.1007/978-1-4615-5199-7_3
Publisher Name: Springer, Boston, MA
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